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git01.mediatek.com / filogic / uboot / acba7c226d735ee221895b950afa9207727e58cc / . / drivers / pinctrl / rockchip / pinctrl-rv1126.c
blob: eefb8b17768b7d695deea74fa0139d2e6083982d [file] [log] [blame]
Jagan Teki28c0adf2022-12-14 23:20:57 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <log.h>
9#include <dm/pinctrl.h>
10#include <regmap.h>
11#include <syscon.h>
12#include <linux/bitops.h>
13#include <dt-bindings/pinctrl/rockchip.h>
14
15#include "pinctrl-rockchip.h"
16
17static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
18 {
19 .num = 0,
20 .pin = 20,
21 .reg = 0x10000,
22 .bit = 0,
23 .mask = 0xf
24 },
25 {
26 .num = 0,
27 .pin = 21,
28 .reg = 0x10000,
29 .bit = 4,
30 .mask = 0xf
31 },
32 {
33 .num = 0,
34 .pin = 22,
35 .reg = 0x10000,
36 .bit = 8,
37 .mask = 0xf
38 },
39 {
40 .num = 0,
41 .pin = 23,
42 .reg = 0x10000,
43 .bit = 12,
44 .mask = 0xf
45 },
46};
47
48static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
49 MR_TOPGRF(RK_GPIO3, RK_PD2, 1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
50 MR_TOPGRF(RK_GPIO3, RK_PB0, 3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
51
52 MR_TOPGRF(RK_GPIO0, RK_PD4, 4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
53 MR_TOPGRF(RK_GPIO1, RK_PD5, 2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
54 MR_TOPGRF(RK_GPIO2, RK_PC7, 6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
55
56 MR_TOPGRF(RK_GPIO1, RK_PD0, 1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
57 MR_TOPGRF(RK_GPIO2, RK_PB3, 2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
58
59 MR_TOPGRF(RK_GPIO3, RK_PD4, 2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
60 MR_TOPGRF(RK_GPIO3, RK_PC0, 3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
61
62 MR_TOPGRF(RK_GPIO3, RK_PC6, 1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
63 MR_TOPGRF(RK_GPIO2, RK_PD1, 3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
64
65 MR_TOPGRF(RK_GPIO3, RK_PA4, 5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
66 MR_TOPGRF(RK_GPIO2, RK_PD4, 7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
67 MR_TOPGRF(RK_GPIO1, RK_PD6, 3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
68
69 MR_TOPGRF(RK_GPIO3, RK_PA0, 7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
70 MR_TOPGRF(RK_GPIO4, RK_PA0, 4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
71
72 MR_TOPGRF(RK_GPIO2, RK_PA5, 7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
73 MR_TOPGRF(RK_GPIO3, RK_PB0, 5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
74 MR_TOPGRF(RK_GPIO1, RK_PD0, 4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
75
76 MR_TOPGRF(RK_GPIO3, RK_PC0, 5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
77 MR_TOPGRF(RK_GPIO1, RK_PC6, 3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
78 MR_TOPGRF(RK_GPIO2, RK_PD5, 6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
79
80 MR_TOPGRF(RK_GPIO3, RK_PC0, 2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
81 MR_TOPGRF(RK_GPIO2, RK_PB7, 2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
82
83 MR_TOPGRF(RK_GPIO3, RK_PA1, 3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
84 MR_TOPGRF(RK_GPIO3, RK_PA7, 5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
85
86 MR_TOPGRF(RK_GPIO3, RK_PA4, 6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */
87 MR_TOPGRF(RK_GPIO2, RK_PD7, 5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */
88
89 MR_TOPGRF(RK_GPIO3, RK_PA5, 6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */
90 MR_TOPGRF(RK_GPIO2, RK_PD6, 5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */
91
92 MR_TOPGRF(RK_GPIO3, RK_PA6, 6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */
93 MR_TOPGRF(RK_GPIO2, RK_PD5, 5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */
94
95 MR_TOPGRF(RK_GPIO3, RK_PA7, 6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
96 MR_TOPGRF(RK_GPIO3, RK_PA1, 5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
97
98 MR_TOPGRF(RK_GPIO1, RK_PA5, 3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
99 MR_TOPGRF(RK_GPIO3, RK_PA2, 1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
100
101 MR_TOPGRF(RK_GPIO3, RK_PC6, 3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
102 MR_TOPGRF(RK_GPIO1, RK_PA7, 2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
103 MR_TOPGRF(RK_GPIO3, RK_PA0, 4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
104
105 MR_TOPGRF(RK_GPIO3, RK_PA4, 4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
106 MR_TOPGRF(RK_GPIO2, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
107 MR_TOPGRF(RK_GPIO1, RK_PD5, 3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
108
109 MR_TOPGRF(RK_GPIO3, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
110 MR_TOPGRF(RK_GPIO2, RK_PB0, 4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
111 MR_TOPGRF(RK_GPIO2, RK_PA0, 3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
112
113 MR_PMUGRF(RK_GPIO0, RK_PB6, 3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */
114 MR_PMUGRF(RK_GPIO2, RK_PB3, 5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */
115
116 MR_PMUGRF(RK_GPIO0, RK_PB7, 3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */
117 MR_PMUGRF(RK_GPIO2, RK_PB2, 5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */
118
119 MR_PMUGRF(RK_GPIO0, RK_PC0, 3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */
120 MR_PMUGRF(RK_GPIO2, RK_PB1, 5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */
121
122 MR_PMUGRF(RK_GPIO0, RK_PC1, 3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
123 MR_PMUGRF(RK_GPIO2, RK_PB0, 5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
124
125 MR_PMUGRF(RK_GPIO0, RK_PC2, 3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */
126 MR_PMUGRF(RK_GPIO2, RK_PA7, 5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */
127
128 MR_PMUGRF(RK_GPIO0, RK_PC3, 3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */
129 MR_PMUGRF(RK_GPIO2, RK_PA6, 5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */
130
131 MR_PMUGRF(RK_GPIO0, RK_PB2, 3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */
132 MR_PMUGRF(RK_GPIO2, RK_PD4, 5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */
133
134 MR_PMUGRF(RK_GPIO0, RK_PB1, 3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
135 MR_PMUGRF(RK_GPIO3, RK_PA0, 5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
136
137 MR_PMUGRF(RK_GPIO0, RK_PB0, 1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
138 MR_PMUGRF(RK_GPIO2, RK_PA1, 1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
139 MR_PMUGRF(RK_GPIO2, RK_PB2, 6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
140
141 MR_PMUGRF(RK_GPIO0, RK_PB6, 2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
142 MR_PMUGRF(RK_GPIO1, RK_PD0, 5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
143 MR_PMUGRF(RK_GPIO0, RK_PC3, 1, 0x0118, RK_GENMASK_VAL(4, 4, 1)), /* I2C2 */
144};
145
146static int rv1126_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
147{
148 struct rockchip_pinctrl_priv *priv = bank->priv;
149 int iomux_num = (pin / 8);
150 struct regmap *regmap;
151 int reg, ret, mask, mux_type;
152 u8 bit;
153 u32 data;
154
155 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
156
157 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
158 regmap = priv->regmap_pmu;
159 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
160 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
161 else
162 regmap = priv->regmap_base;
163
164 /* get basic quadrupel of mux registers and the correct reg inside */
165 mux_type = bank->iomux[iomux_num].type;
166 reg = bank->iomux[iomux_num].offset;
167 if (mux_type & IOMUX_WIDTH_4BIT) {
168 if ((pin % 8) >= 4)
169 reg += 0x4;
170 bit = (pin % 4) * 4;
171 mask = 0xf;
172 } else {
173 bit = (pin % 8) * 2;
174 mask = 0x3;
175 }
176
177 if (bank->recalced_mask & BIT(pin))
178 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
179
180 data = (mask << (bit + 16));
181 data |= (mux & mask) << bit;
182 ret = regmap_write(regmap, reg, data);
183
184 return ret;
185}
186
187#define RV1126_PULL_PMU_OFFSET 0x40
188#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
189#define RV1126_PULL_PINS_PER_REG 8
190#define RV1126_PULL_BITS_PER_PIN 2
191#define RV1126_PULL_BANK_STRIDE 16
192#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
193
194static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
195 int pin_num, struct regmap **regmap,
196 int *reg, u8 *bit)
197{
198 struct rockchip_pinctrl_priv *priv = bank->priv;
199
200 /* The first 24 pins of the first bank are located in PMU */
201 if (bank->bank_num == 0) {
202 if (RV1126_GPIO_C4_D7(pin_num)) {
203 *regmap = priv->regmap_base;
204 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
205 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
206 *bit = pin_num % RV1126_PULL_PINS_PER_REG;
207 *bit *= RV1126_PULL_BITS_PER_PIN;
208 return;
209 }
210 *regmap = priv->regmap_pmu;
211 *reg = RV1126_PULL_PMU_OFFSET;
212 } else {
213 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
214 *regmap = priv->regmap_base;
215 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
216 }
217
218 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
219 *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
220 *bit *= RV1126_PULL_BITS_PER_PIN;
221}
222
223static int rv1126_set_pull(struct rockchip_pin_bank *bank,
224 int pin_num, int pull)
225{
226 struct regmap *regmap;
227 int reg, ret;
228 u8 bit, type;
229 u32 data;
230
231 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
232 return -EOPNOTSUPP;
233
234 rv1126_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
235 type = bank->pull_type[pin_num / 8];
236 ret = rockchip_translate_pull_value(type, pull);
237 if (ret < 0) {
238 debug("unsupported pull setting %d\n", pull);
239 return ret;
240 }
241
242 /* enable the write to the equivalent lower bits */
243 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
244
245 data |= (ret << bit);
246 ret = regmap_write(regmap, reg, data);
247
248 return ret;
249}
250
251#define RV1126_DRV_PMU_OFFSET 0x20
252#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
253#define RV1126_DRV_BITS_PER_PIN 4
254#define RV1126_DRV_PINS_PER_REG 4
255#define RV1126_DRV_BANK_STRIDE 32
256
257static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
258 int pin_num, struct regmap **regmap,
259 int *reg, u8 *bit)
260{
261 struct rockchip_pinctrl_priv *priv = bank->priv;
262
263 /* The first 24 pins of the first bank are located in PMU */
264 if (bank->bank_num == 0) {
265 if (RV1126_GPIO_C4_D7(pin_num)) {
266 *regmap = priv->regmap_base;
267 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
268 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
269 *reg -= 0x4;
270 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
271 *bit *= RV1126_DRV_BITS_PER_PIN;
272 return;
273 }
274 *regmap = priv->regmap_pmu;
275 *reg = RV1126_DRV_PMU_OFFSET;
276 } else {
277 *regmap = priv->regmap_base;
278 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
279 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
280 }
281
282 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
283 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
284 *bit *= RV1126_DRV_BITS_PER_PIN;
285}
286
287static int rv1126_set_drive(struct rockchip_pin_bank *bank,
288 int pin_num, int strength)
289{
290 struct regmap *regmap;
291 int reg;
292 u32 data;
293 u8 bit;
294
295 rv1126_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
296
297 /* enable the write to the equivalent lower bits */
298 data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
299 data |= (strength << bit);
300
301 return regmap_write(regmap, reg, data);
302}
303
304#define RV1126_SCHMITT_PMU_OFFSET 0x60
305#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
306#define RV1126_SCHMITT_BANK_STRIDE 16
307#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
308#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
309
310static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
311 int pin_num,
312 struct regmap **regmap,
313 int *reg, u8 *bit)
314{
315 struct rockchip_pinctrl_priv *priv = bank->priv;
316 int pins_per_reg;
317
318 if (bank->bank_num == 0) {
319 if (RV1126_GPIO_C4_D7(pin_num)) {
320 *regmap = priv->regmap_base;
321 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
322 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
323 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
324 return 0;
325 }
326 *regmap = priv->regmap_pmu;
327 *reg = RV1126_SCHMITT_PMU_OFFSET;
328 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
329 } else {
330 *regmap = priv->regmap_base;
331 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
332 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
333 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
334 }
335 *reg += ((pin_num / pins_per_reg) * 4);
336 *bit = pin_num % pins_per_reg;
337
338 return 0;
339}
340
341static int rv1126_set_schmitt(struct rockchip_pin_bank *bank,
342 int pin_num, int enable)
343{
344 struct regmap *regmap;
345 int reg;
346 u8 bit;
347 u32 data;
348
349 rv1126_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
350 /* enable the write to the equivalent lower bits */
351 data = BIT(bit + 16) | (enable << bit);
352
353 return regmap_write(regmap, reg, data);
354}
355
356static struct rockchip_pin_bank rv1126_pin_banks[] = {
357 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
358 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
359 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
360 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
361 IOMUX_WIDTH_4BIT),
362 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
363 IOMUX_WIDTH_4BIT,
364 IOMUX_WIDTH_4BIT,
365 IOMUX_WIDTH_4BIT,
366 IOMUX_WIDTH_4BIT,
367 0x10010, 0x10018, 0x10020, 0x10028),
368 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
369 IOMUX_WIDTH_4BIT,
370 IOMUX_WIDTH_4BIT,
371 IOMUX_WIDTH_4BIT,
372 IOMUX_WIDTH_4BIT),
373 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
374 IOMUX_WIDTH_4BIT,
375 IOMUX_WIDTH_4BIT,
376 IOMUX_WIDTH_4BIT,
377 IOMUX_WIDTH_4BIT),
378 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
379 IOMUX_WIDTH_4BIT, 0, 0, 0),
380};
381
382static const struct rockchip_pin_ctrl rv1126_pin_ctrl = {
383 .pin_banks = rv1126_pin_banks,
384 .nr_banks = ARRAY_SIZE(rv1126_pin_banks),
385 .nr_pins = 130,
386 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
387 .pmu_mux_offset = 0x0,
388 .iomux_routes = rv1126_mux_route_data,
389 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
390 .iomux_recalced = rv1126_mux_recalced_data,
391 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
392 .set_mux = rv1126_set_mux,
393 .set_pull = rv1126_set_pull,
394 .set_drive = rv1126_set_drive,
395 .set_schmitt = rv1126_set_schmitt,
396};
397
398static const struct udevice_id rv1126_pinctrl_ids[] = {
399 {
400 .compatible = "rockchip,rv1126-pinctrl",
401 .data = (ulong)&rv1126_pin_ctrl
402 },
403 { }
404};
405
406U_BOOT_DRIVER(pinctrl_rv1126) = {
407 .name = "rockchip_rv1126_pinctrl",
408 .id = UCLASS_PINCTRL,
409 .of_match = rv1126_pinctrl_ids,
410 .priv_auto = sizeof(struct rockchip_pinctrl_priv),
411 .ops = &rockchip_pinctrl_ops,
412#if !CONFIG_IS_ENABLED(OF_PLATDATA)
413 .bind = dm_scan_fdt_dev,
414#endif
415 .probe = rockchip_pinctrl_probe,
416};