blob: db7b1668d99a60ecd3992f0e090b37a7f0c23e00 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkd62589d2002-08-20 21:10:12 +00002/*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkd62589d2002-08-20 21:10:12 +00005 */
6
7/*
8 * This file contains all the macros and symbols which define
9 * a PowerPC assembly language environment.
10 */
11#ifndef __PPC_ASM_TMPL__
12#define __PPC_ASM_TMPL__
13
Scott Woodf21e7582015-04-07 20:20:00 -050014#include <config.h>
15
wdenkd62589d2002-08-20 21:10:12 +000016/***************************************************************************
17 *
18 * These definitions simplify the ugly declarations necessary for GOT
19 * definitions.
20 *
21 * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
22 *
Heiko Schocherbb4bd672010-06-17 07:01:40 +020023 * Uses r12 to access the GOT
wdenkd62589d2002-08-20 21:10:12 +000024 */
25
26#define START_GOT \
27 .section ".got2","aw"; \
28.LCTOC1 = .+32768
29
30#define END_GOT \
31 .text
32
33#define GET_GOT \
34 bl 1f ; \
35 .text 2 ; \
360: .long .LCTOC1-1f ; \
37 .text ; \
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100381: mflr r12 ; \
39 lwz r0,0b-1b(r12) ; \
40 add r12,r0,r12 ;
wdenkd62589d2002-08-20 21:10:12 +000041
42#define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME
43
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +010044#define GOT(NAME) .L_ ## NAME (r12)
wdenkd62589d2002-08-20 21:10:12 +000045
46
47/***************************************************************************
48 * Register names
49 */
50#define r0 0
51#define r1 1
52#define r2 2
53#define r3 3
54#define r4 4
55#define r5 5
56#define r6 6
57#define r7 7
58#define r8 8
59#define r9 9
60#define r10 10
61#define r11 11
62#define r12 12
63#define r13 13
64#define r14 14
65#define r15 15
66#define r16 16
67#define r17 17
68#define r18 18
69#define r19 19
70#define r20 20
71#define r21 21
72#define r22 22
73#define r23 23
74#define r24 24
75#define r25 25
76#define r26 26
77#define r27 27
78#define r28 28
79#define r29 29
80#define r30 30
81#define r31 31
82
Christophe Leroyb3510fb2018-03-16 17:20:41 +010083#if defined(CONFIG_MPC8xx)
Christophe Leroy069fa832017-07-06 10:23:22 +020084
85/* Some special registers */
86
87#define ICR 148 /* Interrupt Cause Register (37-44) */
88#define DER 149
89#define COUNTA 150 /* Breakpoint Counter (37-44) */
90#define COUNTB 151 /* Breakpoint Counter (37-44) */
91#define LCTRL1 156 /* Load/Store Support (37-40) */
92#define LCTRL2 157 /* Load/Store Support (37-41) */
93#define ICTRL 158
94
Christophe Leroyb3510fb2018-03-16 17:20:41 +010095#endif /* CONFIG_MPC8xx */
Christophe Leroy069fa832017-07-06 10:23:22 +020096
97
Christophe Leroyb3510fb2018-03-16 17:20:41 +010098#if defined(CONFIG_MPC8xx)
Christophe Leroy069fa832017-07-06 10:23:22 +020099
100/* Registers in the processor's internal memory map that we use.
101*/
102#define SYPCR 0x00000004
103#define BR0 0x00000100
104#define OR0 0x00000104
105#define BR1 0x00000108
106#define OR1 0x0000010c
107#define BR2 0x00000110
108#define OR2 0x00000114
109#define BR3 0x00000118
110#define OR3 0x0000011c
111#define BR4 0x00000120
112#define OR4 0x00000124
113
114#define MAR 0x00000164
115#define MCR 0x00000168
116#define MAMR 0x00000170
117#define MBMR 0x00000174
118#define MSTAT 0x00000178
119#define MPTPR 0x0000017a
120#define MDR 0x0000017c
121
122#define TBSCR 0x00000200
123#define TBREFF0 0x00000204
124
125#define PLPRCR 0x00000284
126
127#endif
128
wdenkd62589d2002-08-20 21:10:12 +0000129#define curptr r2
130
131#define SYNC \
132 sync; \
133 isync
134
135/*
136 * Macros for storing registers into and loading registers from
137 * exception frames.
138 */
139#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
140#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
141#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
142#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
143#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
144#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
145#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
146#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
147#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
148#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
149
150/*
151 * GCC sometimes accesses words at negative offsets from the stack
152 * pointer, although the SysV ABI says it shouldn't. To cope with
153 * this, we leave this much untouched space on the stack on exception
154 * entry.
155 */
156#define STACK_UNDERHEAD 64
157
158/*
159 * Exception entry code. This code runs with address translation
160 * turned off, i.e. using physical addresses.
161 * We assume sprg3 has the physical address of the current
162 * task's thread_struct.
163 */
Grzegorz Bernacki837bc5b2007-06-15 11:19:28 +0200164#define EXCEPTION_PROLOG(reg1, reg2) \
wdenkd62589d2002-08-20 21:10:12 +0000165 mtspr SPRG0,r20; \
166 mtspr SPRG1,r21; \
167 mfcr r20; \
168 subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
169 stw r20,_CCR(r21); /* save registers */ \
170 stw r22,GPR22(r21); \
171 stw r23,GPR23(r21); \
172 mfspr r20,SPRG0; \
173 stw r20,GPR20(r21); \
174 mfspr r22,SPRG1; \
175 stw r22,GPR21(r21); \
176 mflr r20; \
177 stw r20,_LINK(r21); \
178 mfctr r22; \
179 stw r22,_CTR(r21); \
180 mfspr r20,XER; \
181 stw r20,_XER(r21); \
Rafal Jaworowskid6520bc2007-07-19 17:12:28 +0200182 mfspr r20, DAR_DEAR; \
Grzegorz Bernacki837bc5b2007-06-15 11:19:28 +0200183 stw r20,_DAR(r21); \
184 mfspr r22,reg1; \
185 mfspr r23,reg2; \
wdenkd62589d2002-08-20 21:10:12 +0000186 stw r0,GPR0(r21); \
187 stw r1,GPR1(r21); \
188 stw r2,GPR2(r21); \
189 stw r1,0(r21); \
190 mr r1,r21; /* set new kernel sp */ \
191 SAVE_4GPRS(3, r21);
192/*
193 * Note: code which follows this uses cr0.eq (set if from kernel),
194 * r21, r22 (SRR0), and r23 (SRR1).
195 */
196
197/*
wdenkd62589d2002-08-20 21:10:12 +0000198 * Exception vectors.
199 *
200 * The data words for `hdlr' and `int_return' are initialized with
201 * OFFSET values only; they must be relocated first before they can
202 * be used!
203 */
Joakim Tjernlund4ff6bc02010-01-19 14:41:55 +0100204#define COPY_EE(d, s) rlwimi d,s,0,16,16
205#define NOCOPY(d, s)
Scott Woodf21e7582015-04-07 20:20:00 -0500206
207#ifdef CONFIG_E500
208#define EXC_XFER_TEMPLATE(n, label, hdlr, msr, copyee) \
209 stw r22,_NIP(r21); \
210 stw r23,_MSR(r21); \
211 li r23,n; \
212 stw r23,TRAP(r21); \
213 li r20,msr; \
214 copyee(r20,r23); \
215 rlwimi r20,r23,0,25,25; \
216 mtmsr r20; \
217 bl 1f; \
2181: mflr r23; \
219 addis r23,r23,(hdlr - 1b)@ha; \
220 addi r23,r23,(hdlr - 1b)@l; \
221 b transfer_to_handler
222
223#define STD_EXCEPTION(n, label, hdlr) \
mario.six@gdsys.ccd5928cd2016-04-05 15:05:37 +0200224.align 4; \
Scott Woodf21e7582015-04-07 20:20:00 -0500225label: \
226 EXCEPTION_PROLOG(SRR0, SRR1); \
227 addi r3,r1,STACK_FRAME_OVERHEAD; \
228 EXC_XFER_TEMPLATE(n, label, hdlr, MSR_KERNEL, NOCOPY) \
229
230#define CRIT_EXCEPTION(n, label, hdlr) \
mario.six@gdsys.ccd5928cd2016-04-05 15:05:37 +0200231.align 4; \
Scott Woodf21e7582015-04-07 20:20:00 -0500232label: \
233 EXCEPTION_PROLOG(CSRR0, CSRR1); \
234 addi r3,r1,STACK_FRAME_OVERHEAD; \
235 EXC_XFER_TEMPLATE(n, label, hdlr, \
236 MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
237
238#define MCK_EXCEPTION(n, label, hdlr) \
mario.six@gdsys.ccd5928cd2016-04-05 15:05:37 +0200239.align 4; \
Scott Woodf21e7582015-04-07 20:20:00 -0500240label: \
241 EXCEPTION_PROLOG(MCSRR0, MCSRR1); \
242 addi r3,r1,STACK_FRAME_OVERHEAD; \
243 EXC_XFER_TEMPLATE(n, label, hdlr, \
244 MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
245
246#else /* !E500 */
247
Joakim Tjernlund4ff6bc02010-01-19 14:41:55 +0100248#define EXC_XFER_TEMPLATE(label, hdlr, msr, copyee) \
249 bl 1f; \
2501: mflr r20; \
251 lwz r20,(.L_ ## label)-1b+8(r20); \
252 mtlr r20; \
253 li r20,msr; \
254 copyee(r20,r23); \
wdenkd62589d2002-08-20 21:10:12 +0000255 rlwimi r20,r23,0,25,25; \
Wolfgang Denk09675ef2007-06-20 18:14:24 +0200256 blrl; \
wdenkd62589d2002-08-20 21:10:12 +0000257.L_ ## label : \
Grzegorz Bernacki837bc5b2007-06-15 11:19:28 +0200258 .long hdlr - _start + _START_OFFSET; \
Joakim Tjernlund4ff6bc02010-01-19 14:41:55 +0100259 .long int_return - _start + _START_OFFSET; \
260 .long transfer_to_handler - _start + _START_OFFSET
261
262#define STD_EXCEPTION(n, label, hdlr) \
263 . = n; \
264label: \
265 EXCEPTION_PROLOG(SRR0, SRR1); \
266 addi r3,r1,STACK_FRAME_OVERHEAD; \
267 EXC_XFER_TEMPLATE(label, hdlr, MSR_KERNEL, NOCOPY) \
wdenkd62589d2002-08-20 21:10:12 +0000268
Grzegorz Bernacki837bc5b2007-06-15 11:19:28 +0200269#define CRIT_EXCEPTION(n, label, hdlr) \
Wolfgang Denk09675ef2007-06-20 18:14:24 +0200270 . = n; \
Grzegorz Bernacki837bc5b2007-06-15 11:19:28 +0200271label: \
Rafal Jaworowski06244e42007-06-22 14:58:04 +0200272 EXCEPTION_PROLOG(CSRR0, CSRR1); \
Wolfgang Denk09675ef2007-06-20 18:14:24 +0200273 addi r3,r1,STACK_FRAME_OVERHEAD; \
Joakim Tjernlund4ff6bc02010-01-19 14:41:55 +0100274 EXC_XFER_TEMPLATE(label, hdlr, \
275 MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
wdenkd62589d2002-08-20 21:10:12 +0000276
Grzegorz Bernacki837bc5b2007-06-15 11:19:28 +0200277#define MCK_EXCEPTION(n, label, hdlr) \
Wolfgang Denk09675ef2007-06-20 18:14:24 +0200278 . = n; \
Grzegorz Bernacki837bc5b2007-06-15 11:19:28 +0200279label: \
Wolfgang Denk09675ef2007-06-20 18:14:24 +0200280 EXCEPTION_PROLOG(MCSRR0, MCSRR1); \
Wolfgang Denk09675ef2007-06-20 18:14:24 +0200281 addi r3,r1,STACK_FRAME_OVERHEAD; \
Joakim Tjernlund4ff6bc02010-01-19 14:41:55 +0100282 EXC_XFER_TEMPLATE(label, hdlr, \
283 MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \
wdenkd62589d2002-08-20 21:10:12 +0000284
Scott Woodf21e7582015-04-07 20:20:00 -0500285#endif /* !E500 */
wdenkd62589d2002-08-20 21:10:12 +0000286#endif /* __PPC_ASM_TMPL__ */