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git01.mediatek.com / filogic / uboot / ac73f47476abd12c12830c464a096d0313e82d11 / . / configs / stm32746g-eval_spl_defconfig
blob: f9711bedd7d2c9dc47ffad4e27a650dc506e4659 [file] [log] [blame]
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_STM32=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]3CONFIG_TEXT_BASE=0x08009000
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]4CONFIG_SYS_MALLOC_LEN=0x100000
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]5CONFIG_SPL_GPIO=y
6CONFIG_SPL_LIBCOMMON_SUPPORT=y
7CONFIG_SPL_LIBGENERIC_SUPPORT=y
8CONFIG_NR_DRAM_BANKS=1
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]9CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
10CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]11CONFIG_ENV_SIZE=0x2000
12CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval"
13CONFIG_SPL_TEXT_BASE=0x8000000
Tom Rinia77d6f82023-05-01 11:50:26 -0400[diff] [blame]14CONFIG_OF_LIBFDT_OVERLAY=y
Tom Rini3d2b97c2023-05-29 10:43:26 -0400[diff] [blame]15CONFIG_SYS_MONITOR_LEN=524288
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]16CONFIG_SPL_SERIAL=y
17CONFIG_SPL_DRIVERS_MISC=y
Patrice Chotardb0363352022-09-20 18:04:32 +0200[diff] [blame]18CONFIG_SPL_SIZE_LIMIT=0x9000
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]19CONFIG_STM32F7=y
20CONFIG_TARGET_STM32F746_DISCO=y
21CONFIG_SPL=y
Patrice Chotardb0363352022-09-20 18:04:32 +0200[diff] [blame]22CONFIG_SYS_LOAD_ADDR=0x8009000
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]23CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
Tom Riniadb7a192023-03-27 13:39:17 -0400[diff] [blame]24CONFIG_DISTRO_DEFAULTS=y
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]25CONFIG_BOOTDELAY=3
26CONFIG_AUTOBOOT_KEYED=y
27CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
28CONFIG_AUTOBOOT_STOP_STR=" "
29CONFIG_USE_BOOTARGS=y
30CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
31# CONFIG_DISPLAY_CPUINFO is not set
32CONFIG_BOARD_LATE_INIT=y
Patrice Chotardb0363352022-09-20 18:04:32 +0200[diff] [blame]33CONFIG_SPL_PAD_TO=0x9000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]34CONFIG_SPL_NO_BSS_LIMIT=y
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]35CONFIG_SPL_BOARD_INIT=y
36CONFIG_SPL_SYS_MALLOC_SIMPLE=y
Sean Anderson34ec1662023-11-04 16:37:47 -0400[diff] [blame]37CONFIG_SPL_MTD=y
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]38CONFIG_SPL_XIP_SUPPORT=y
Simon Glass259cdb42023-09-26 08:14:17 -0600[diff] [blame]39CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x80c0000
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]40CONFIG_SPL_DM_RESET=y
Tom Rinic4359852023-10-02 10:35:27 -0400[diff] [blame]41CONFIG_SYS_PROMPT="U-Boot > "
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]42CONFIG_SYS_PBSIZE=1050
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]43CONFIG_CMD_GPT=y
44# CONFIG_RANDOM_UUID is not set
45CONFIG_CMD_MMC=y
46# CONFIG_CMD_SETEXPR is not set
47CONFIG_CMD_SNTP=y
48CONFIG_CMD_DNS=y
49CONFIG_CMD_LINK_LOCAL=y
50CONFIG_CMD_BMP=y
51CONFIG_CMD_CACHE=y
52CONFIG_CMD_TIMER=y
53# CONFIG_ISO_PARTITION is not set
54CONFIG_OF_CONTROL=y
55CONFIG_SPL_OF_CONTROL=y
56CONFIG_SYS_RELOC_GD_ENV_ADDR=y
57CONFIG_NET_RANDOM_ETHADDR=y
58CONFIG_NETCONSOLE=y
59CONFIG_SPL_DM=y
60CONFIG_SPL_DM_SEQ_ALIAS=y
61CONFIG_SPL_OF_TRANSLATE=y
62CONFIG_SPL_CLK=y
63CONFIG_ARM_PL180_MMCI=y
64CONFIG_MTD=y
65CONFIG_DM_MTD=y
66CONFIG_MTD_NOR_FLASH=y
67CONFIG_STM32_FLASH=y
Tom Rinid38112c2022-07-23 13:05:04 -0400[diff] [blame]68CONFIG_SYS_MAX_FLASH_SECT=8
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]69CONFIG_DM_SPI_FLASH=y
70CONFIG_SPI_FLASH_MACRONIX=y
71CONFIG_SPI_FLASH_STMICRO=y
72CONFIG_PHY_SMSC=y
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]73CONFIG_ETH_DESIGNWARE=y
Tom Rini7ac21a32022-06-15 12:03:43 -0400[diff] [blame]74CONFIG_DW_ALTDESCRIPTOR=y
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]75CONFIG_MII=y
76# CONFIG_PINCTRL_FULL is not set
77CONFIG_SPL_PINCTRL=y
78CONFIG_SPL_RAM=y
79CONFIG_SPECIFY_CONSOLE_INDEX=y
80CONFIG_SPI=y
81CONFIG_DM_SPI=y
82CONFIG_STM32_QSPI=y
83CONFIG_SPL_TIMER=y
Simon Glass52cb5042022-10-18 07:46:31 -0600[diff] [blame]84CONFIG_VIDEO=y
Patrice Chotardcad450c2022-04-27 13:54:00 +0200[diff] [blame]85CONFIG_BACKLIGHT_GPIO=y
86CONFIG_VIDEO_STM32=y
87CONFIG_VIDEO_STM32_MAX_XRES=480
88CONFIG_VIDEO_STM32_MAX_YRES=640
89CONFIG_SPLASH_SCREEN=y
90CONFIG_SPLASH_SCREEN_ALIGN=y
91CONFIG_VIDEO_BMP_RLE8=y
92CONFIG_BMP_16BPP=y
93CONFIG_BMP_24BPP=y
94CONFIG_BMP_32BPP=y