| Andy Shevchenko | d31315d | 2017-07-06 14:41:53 +0300 | [diff] [blame] | 1 | if TARGET_EDISON |
| 2 | |
| 3 | config SYS_BOARD |
| 4 | default "edison" |
| 5 | |
| 6 | config SYS_VENDOR |
| 7 | default "intel" |
| 8 | |
| 9 | config SYS_SOC |
| 10 | default "tangier" |
| 11 | |
| 12 | config SYS_CONFIG_NAME |
| 13 | default "edison" |
| 14 | |
| Andy Shevchenko | dfba072 | 2020-09-08 16:57:22 +0300 | [diff] [blame] | 15 | config SYS_MALLOC_LEN |
| 16 | default 0x08000000 |
| 17 | |
| Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 18 | config TEXT_BASE |
| Andy Shevchenko | d31315d | 2017-07-06 14:41:53 +0300 | [diff] [blame] | 19 | default 0x01101000 |
| 20 | |
| Andy Shevchenko | 6391f07 | 2017-10-03 14:55:08 +0300 | [diff] [blame] | 21 | config ROM_TABLE_ADDR |
| 22 | default 0x0e4500 |
| 23 | |
| 24 | config ROM_TABLE_SIZE |
| 25 | default 0x007b00 |
| 26 | |
| Andy Shevchenko | d31315d | 2017-07-06 14:41:53 +0300 | [diff] [blame] | 27 | config BOARD_SPECIFIC_OPTIONS # dummy |
| 28 | def_bool y |
| 29 | select X86_LOAD_FROM_32_BIT |
| 30 | select INTEL_MID |
| 31 | select INTEL_TANGIER |
| 32 | select BOARD_LATE_INIT |
| 33 | select MD5 |
| Andy Shevchenko | 6e4afff | 2020-12-03 17:40:11 +0200 | [diff] [blame] | 34 | imply BINMAN |
| Andy Shevchenko | d31315d | 2017-07-06 14:41:53 +0300 | [diff] [blame] | 35 | |
| 36 | endif |