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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek04b7e622015-01-15 10:01:51 +01002/*
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
Michal Simek04b7e622015-01-15 10:01:51 +01005 */
6
7#include <common.h>
Michal Simek0ca55572015-04-15 14:59:19 +02008#include <asm/arch/clk.h>
Michal Simek04b7e622015-01-15 10:01:51 +01009#include <asm/arch/hardware.h>
10#include <asm/arch/sys_proto.h>
11
12DECLARE_GLOBAL_DATA_PTR;
13
Michal Simekc23d3f82015-11-05 08:34:35 +010014unsigned long zynqmp_get_system_timer_freq(void)
15{
16 u32 ver = zynqmp_get_silicon_version();
17
18 switch (ver) {
Michal Simekc23d3f82015-11-05 08:34:35 +010019 case ZYNQMP_CSU_VERSION_QEMU:
20 return 50000000;
21 }
22
23 return 100000000;
24}
25
Michal Simek04b7e622015-01-15 10:01:51 +010026#ifdef CONFIG_CLOCKS
27/**
28 * set_cpu_clk_info() - Initialize clock framework
29 * Always returns zero.
30 *
31 * This function is called from common code after relocation and sets up the
32 * clock framework. The framework must not be used before this function had been
33 * called.
34 */
35int set_cpu_clk_info(void)
36{
37 gd->cpu_clk = get_tbclk();
38
Michal Simekdaf315f2018-05-14 15:33:22 +020039 gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
Michal Simek04b7e622015-01-15 10:01:51 +010040
41 gd->bd->bi_dsp_freq = 0;
42
43 return 0;
44}
45#endif