Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2007 Freescale Semiconductor, Inc. |
| 4 | * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com |
| 5 | * |
| 6 | * Authors: Nick.Spence@freescale.com |
| 7 | * Wilson.Lo@freescale.com |
| 8 | * scottwood@freescale.com |
| 9 | * |
| 10 | * This files is mostly identical to the original from |
| 11 | * board\freescale\mpc8315erdb\sdram.c |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 12 | */ |
| 13 | |
Mario Six | 0486138 | 2019-03-29 10:18:09 +0100 | [diff] [blame] | 14 | #ifndef CONFIG_MPC83XX_SDRAM |
| 15 | |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 16 | #include <common.h> |
Simon Glass | 8e16b1e | 2019-12-28 10:45:05 -0700 | [diff] [blame] | 17 | #include <init.h> |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 18 | #include <mpc83xx.h> |
| 19 | #include <spd_sdram.h> |
| 20 | |
| 21 | #include <asm/bitops.h> |
| 22 | #include <asm/io.h> |
| 23 | |
| 24 | #include <asm/processor.h> |
| 25 | |
| 26 | DECLARE_GLOBAL_DATA_PTR; |
| 27 | |
| 28 | /* Fixed sdram init -- doesn't use serial presence detect. |
| 29 | * |
| 30 | * This is useful for faster booting in configs where the RAM is unlikely |
| 31 | * to be changed, or for things like NAND booting where space is tight. |
| 32 | */ |
| 33 | static long fixed_sdram(void) |
| 34 | { |
| 35 | immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
| 36 | u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; |
| 37 | u32 msize_log2 = __ilog2(msize); |
| 38 | |
| 39 | out_be32(&im->sysconf.ddrlaw[0].bar, |
Mario Six | 805cac1 | 2019-01-21 09:18:16 +0100 | [diff] [blame] | 40 | CONFIG_SYS_SDRAM_BASE & 0xfffff000); |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 41 | out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); |
| 42 | out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); |
| 43 | |
| 44 | out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); |
| 45 | out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); |
| 46 | |
| 47 | /* Currently we use only one CS, so disable the other bank. */ |
| 48 | out_be32(&im->ddr.cs_config[1], 0); |
| 49 | |
| 50 | out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); |
| 51 | out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); |
| 52 | out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); |
| 53 | out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); |
| 54 | out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); |
| 55 | |
| 56 | out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); |
| 57 | out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); |
| 58 | out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); |
| 59 | out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); |
| 60 | |
| 61 | out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); |
| 62 | sync(); |
| 63 | |
| 64 | /* enable DDR controller */ |
| 65 | setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); |
| 66 | sync(); |
| 67 | |
Mario Six | 805cac1 | 2019-01-21 09:18:16 +0100 | [diff] [blame] | 68 | return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 69 | } |
| 70 | |
Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 71 | int dram_init(void) |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 72 | { |
| 73 | immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
| 74 | u32 msize; |
| 75 | |
| 76 | if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 77 | return -ENXIO; |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 78 | |
| 79 | /* DDR SDRAM */ |
| 80 | msize = fixed_sdram(); |
| 81 | |
| 82 | /* return total bus SDRAM size(bytes) -- DDR */ |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 83 | gd->ram_size = msize; |
| 84 | |
| 85 | return 0; |
Dirk Eibach | f74a027 | 2014-11-13 19:21:18 +0100 | [diff] [blame] | 86 | } |
Mario Six | 0486138 | 2019-03-29 10:18:09 +0100 | [diff] [blame] | 87 | |
| 88 | #endif /* !CONFIG_MPC83XX_SDRAM */ |