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git01.mediatek.com / filogic / uboot / ac42bfeb59a1432e3b75487cb1dd9e1ad43a92e6 / . / board / freescale / imx8mq_evk / imx8mq_evk.c
blob: 1ad670b8ccf0081533ec9912056d3c2f97981d4d [file] [log] [blame]
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -0600[diff] [blame]7#include <env.h>
Simon Glassa7b51302019-11-14 12:57:46 -0700[diff] [blame]8#include <init.h>
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]9#include <malloc.h>
10#include <errno.h>
11#include <asm/io.h>
12#include <miiphy.h>
13#include <netdev.h>
14#include <asm/mach-imx/iomux-v3.h>
15#include <asm-generic/gpio.h>
Yangbo Lu73340382019-06-21 11:42:28 +0800[diff] [blame]16#include <fsl_esdhc_imx.h>
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]17#include <mmc.h>
18#include <asm/arch/imx8mq_pins.h>
19#include <asm/arch/sys_proto.h>
20#include <asm/mach-imx/gpio.h>
21#include <asm/mach-imx/mxc_i2c.h>
22#include <asm/arch/clock.h>
23#include <spl.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]24#include <linux/bitops.h>
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]25#include <power/pmic.h>
26#include <power/pfuze100_pmic.h>
27#include "../common/pfuze.h"
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
32
33#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
34
35static iomux_v3_cfg_t const wdog_pads[] = {
36 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
37};
38
39static iomux_v3_cfg_t const uart_pads[] = {
40 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
41 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
42};
43
44int board_early_init_f(void)
45{
46 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
47
48 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
49 set_wdog_reset(wdog);
50
51 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
52
53 return 0;
54}
55
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]56#ifdef CONFIG_FEC_MXC
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]57static int setup_fec(void)
58{
59 struct iomuxc_gpr_base_regs *gpr =
60 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
61
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]62 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
63 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
64 return set_clk_enet(ENET_125MHZ);
65}
66
67int board_phy_config(struct phy_device *phydev)
68{
69 /* enable rgmii rxc skew and phy mode select to RGMII copper */
70 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
71 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
72
73 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
74 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
75
76 if (phydev->drv->config)
77 phydev->drv->config(phydev);
78 return 0;
79}
80#endif
81
82int board_init(void)
83{
84#ifdef CONFIG_FEC_MXC
85 setup_fec();
86#endif
87
88 return 0;
89}
90
91int board_mmc_get_env_dev(int devno)
92{
93 return devno;
94}
95
96int board_late_init(void)
97{
98#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
99 env_set("board_name", "EVK");
100 env_set("board_rev", "iMX8MQ");
101#endif
102
103 return 0;
104}