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git01.mediatek.com / filogic / uboot / ac1633c901b823a0f7c5326627f799030909c958 / . / arch / powerpc / include / asm / config.h
blob: 423a6fb8dc6419d3ef4020086777a9a3510a2011 [file] [log] [blame]
Kumar Gala4c882892009-02-05 20:40:57 -0600[diff] [blame]1/*
Poonam Aggrwal2ba3ee02011-01-13 21:39:27 +0530[diff] [blame]2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Gala4c882892009-02-05 20:40:57 -0600[diff] [blame]3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala4c882892009-02-05 20:40:57 -0600[diff] [blame]5 */
6
7#ifndef _ASM_CONFIG_H_
8#define _ASM_CONFIG_H_
9
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]10#ifdef CONFIG_MPC85xx
11#include <asm/config_mpc85xx.h>
York Sunf0626592013-09-30 09:22:09 -0700[diff] [blame]12#define CONFIG_SYS_FSL_DDR
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]13#endif
14
15#ifdef CONFIG_MPC86xx
16#include <asm/config_mpc86xx.h>
York Sunf0626592013-09-30 09:22:09 -0700[diff] [blame]17#define CONFIG_SYS_FSL_DDR
18#endif
19
20#ifdef CONFIG_MPC83xx
21#define CONFIG_SYS_FSL_DDR
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]22#endif
23
York Sune2cba152012-08-17 09:00:54 +0000[diff] [blame]24#ifndef HWCONFIG_BUFFER_SIZE
25 #define HWCONFIG_BUFFER_SIZE 256
26#endif
27
Mingkai Hu799efd92011-04-26 16:31:16 +0800[diff] [blame]28/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
29#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
30# ifndef CONFIG_HARD_SPI
31# define CONFIG_HARD_SPI
32# endif
33#endif
34
Mike Frysingera0dadf82009-11-03 11:35:59 -0500[diff] [blame]35#define CONFIG_LMB
John Rigbyeea8e692010-10-13 13:57:35 -0600[diff] [blame]36#define CONFIG_SYS_BOOT_RAMDISK_HIGH
37#define CONFIG_SYS_BOOT_GET_CMDLINE
38#define CONFIG_SYS_BOOT_GET_KBD
Mike Frysingera0dadf82009-11-03 11:35:59 -0500[diff] [blame]39
Kumar Gala4cd44a82009-02-05 20:40:58 -0600[diff] [blame]40#ifndef CONFIG_MAX_MEM_MAPPED
York Sune12ce982011-08-26 11:32:44 -0700[diff] [blame]41#if defined(CONFIG_4xx) || \
42 defined(CONFIG_E500) || \
43 defined(CONFIG_MPC86xx) || \
44 defined(CONFIG_E300)
Kumar Gala4cd44a82009-02-05 20:40:58 -0600[diff] [blame]45#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
46#else
Stefan Roesea14295e2009-02-11 09:37:12 +0100[diff] [blame]47#define CONFIG_MAX_MEM_MAPPED (256 << 20)
Kumar Gala4cd44a82009-02-05 20:40:58 -0600[diff] [blame]48#endif
49#endif
50
Peter Tyserbee01682009-07-15 00:01:08 -0500[diff] [blame]51/* Check if boards need to enable FSL DMA engine for SDRAM init */
52#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
53#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
54 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
55 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
Peter Tyserae7a7d42009-06-30 17:15:40 -0500[diff] [blame]56#define CONFIG_FSL_DMA
57#endif
Kumar Gala4c882892009-02-05 20:40:57 -0600[diff] [blame]58#endif
Peter Tyserae7a7d42009-06-30 17:15:40 -0500[diff] [blame]59
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]60#ifndef CONFIG_MAX_CPUS
Kumar Galabb5409c2009-03-19 02:39:17 -0500[diff] [blame]61#define CONFIG_MAX_CPUS 1
Poonam Aggrwal4baef822009-07-31 12:08:14 +0530[diff] [blame]62#endif
63
Peter Tyser7feaacb2009-10-23 15:55:47 -0500[diff] [blame]64/*
65 * Provide a default boot page translation virtual address that lines up with
66 * Freescale's default e500 reset page.
67 */
68#if (defined(CONFIG_E500) && defined(CONFIG_MP))
69#ifndef CONFIG_BPTR_VIRT_ADDR
70#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
71#endif
72#endif
73
Kim Phillipsdef125f2010-06-01 12:24:27 -0500[diff] [blame]74/*
75 * SEC (crypto unit) major compatible version determination
76 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]77#if defined(CONFIG_MPC83xx)
Kim Phillipsdef125f2010-06-01 12:24:27 -0500[diff] [blame]78#define CONFIG_SYS_FSL_SEC_COMPAT 2
79#endif
80
Becky Bruce0d4cee12010-06-17 11:37:20 -0500[diff] [blame]81/* Since so many PPC SOCs have a semi-common LBC, define this here */
82#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
83 defined(CONFIG_MPC83xx)
Dipen Dudhat00c42942011-01-20 16:29:35 +0530[diff] [blame]84#if !defined(CONFIG_FSL_IFC)
Becky Bruce0d4cee12010-06-17 11:37:20 -0500[diff] [blame]85#define CONFIG_FSL_LBC
86#endif
Dipen Dudhat00c42942011-01-20 16:29:35 +0530[diff] [blame]87#endif
Becky Bruce0d4cee12010-06-17 11:37:20 -0500[diff] [blame]88
Andy Fleming422effd2011-04-08 02:10:54 -0500[diff] [blame]89/* The TSEC driver uses the PHYLIB infrastructure */
90#ifndef CONFIG_PHYLIB
91#if defined(CONFIG_TSEC_ENET)
92#define CONFIG_PHYLIB
93
94#include <config_phylib_all_drivers.h>
95#endif /* TSEC_ENET */
96#endif /* !CONFIG_PHYLIB */
97
Kumar Gala2683c532011-04-13 08:37:44 -0500[diff] [blame]98/* The FMAN driver uses the PHYLIB infrastructure */
99#if defined(CONFIG_FMAN_ENET)
100#define CONFIG_PHYLIB
101#endif
102
Albert Aribaud036c6b42010-08-08 05:17:05 +0530[diff] [blame]103/* All PPC boards must swap IDE bytes */
104#define CONFIG_IDE_SWAP_IO
105
Peter Tyserae7a7d42009-06-30 17:15:40 -0500[diff] [blame]106#endif /* _ASM_CONFIG_H_ */