| Simon Glass | ac0cce5 | 2016-03-11 22:07:23 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * From coreboot soc/intel/broadwell/include/soc/lpc.h |
| 3 | * |
| 4 | * Copyright (C) 2016 Google Inc. |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0 |
| 7 | */ |
| 8 | |
| 9 | #ifndef _ASM_ARCH_LPC_H |
| 10 | #define _ASM_ARCH_LPC_H |
| 11 | |
| 12 | #define GEN_PMCON_1 0xa0 |
| 13 | #define SMI_LOCK (1 << 4) |
| 14 | #define GEN_PMCON_2 0xa2 |
| 15 | #define SYSTEM_RESET_STS (1 << 4) |
| 16 | #define THERMTRIP_STS (1 << 3) |
| 17 | #define SYSPWR_FLR (1 << 1) |
| 18 | #define PWROK_FLR (1 << 0) |
| 19 | #define GEN_PMCON_3 0xa4 |
| 20 | #define SUS_PWR_FLR (1 << 14) |
| 21 | #define GEN_RST_STS (1 << 9) |
| 22 | #define RTC_BATTERY_DEAD (1 << 2) |
| 23 | #define PWR_FLR (1 << 1) |
| 24 | #define SLEEP_AFTER_POWER_FAIL (1 << 0) |
| 25 | #define GEN_PMCON_LOCK 0xa6 |
| 26 | #define SLP_STR_POL_LOCK (1 << 2) |
| 27 | #define ACPI_BASE_LOCK (1 << 1) |
| 28 | #define PMIR 0xac |
| 29 | #define PMIR_CF9LOCK (1 << 31) |
| 30 | #define PMIR_CF9GR (1 << 20) |
| 31 | |
| 32 | #endif |