blob: 15cd2330a38109d64a9842fd8b67d1bc0f1fdb6f [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
5
Simon Glassb2c1cac2014-02-26 15:59:21 -07006/ {
7 model = "sandbox";
8 compatible = "sandbox";
9 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060010 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070011
Simon Glassfef72b72014-07-23 06:55:03 -060012 aliases {
13 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060014 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070015 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060016 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060017 gpio1 = &gpio_a;
18 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010019 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070020 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060021 mmc0 = "/mmc0";
22 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070023 pci0 = &pci0;
24 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070025 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -050026 remoteproc1 = &rproc_1;
27 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060028 rtc0 = &rtc_0;
29 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060030 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020031 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070032 testbus3 = "/some-bus";
33 testfdt0 = "/some-bus/c-test@0";
34 testfdt1 = "/some-bus/c-test@1";
35 testfdt3 = "/b-test";
36 testfdt5 = "/some-bus/c-test@5";
37 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020038 fdt-dummy0 = "/translation-test@8000/dev@0,0";
39 fdt-dummy1 = "/translation-test@8000/dev@1,100";
40 fdt-dummy2 = "/translation-test@8000/dev@2,200";
41 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060042 usb0 = &usb_0;
43 usb1 = &usb_1;
44 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020045 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020046 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060047 };
48
Simon Glassed96cde2018-12-10 10:37:33 -070049 audio: audio-codec {
50 compatible = "sandbox,audio-codec";
51 #sound-dai-cells = <1>;
52 };
53
Simon Glassc953aaf2018-12-10 10:37:34 -070054 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060055 reg = <0 0>;
56 compatible = "google,cros-ec-sandbox";
57
58 /*
59 * This describes the flash memory within the EC. Note
60 * that the STM32L flash erases to 0, not 0xff.
61 */
62 flash {
63 image-pos = <0x08000000>;
64 size = <0x20000>;
65 erase-value = <0>;
66
67 /* Information for sandbox */
68 ro {
69 image-pos = <0>;
70 size = <0xf000>;
71 };
72 wp-ro {
73 image-pos = <0xf000>;
74 size = <0x1000>;
75 };
76 rw {
77 image-pos = <0x10000>;
78 size = <0x10000>;
79 };
80 };
81 };
82
Yannick Fertré9712c822019-10-07 15:29:05 +020083 dsi_host: dsi_host {
84 compatible = "sandbox,dsi-host";
85 };
86
Simon Glassb2c1cac2014-02-26 15:59:21 -070087 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -060088 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070089 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -060090 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070091 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -060092 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +010093 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
94 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -070095 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +010096 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
97 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
98 <&gpio_b 7 GPIO_IN 3 2 1>,
99 <&gpio_b 8 GPIO_OUT 3 2 1>,
100 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100101 test3-gpios =
102 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
103 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
104 <&gpio_c 2 GPIO_OUT>,
105 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
106 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
107 <&gpio_c 5 GPIO_IN>;
Simon Glass6df01f92018-12-10 10:37:37 -0700108 int-value = <1234>;
109 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200110 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200111 int-array = <5678 9123 4567>;
Simon Glass515dcff2020-02-06 09:55:00 -0700112 interrupts-extended = <&irq 3 0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700113 };
114
115 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600116 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700117 compatible = "not,compatible";
118 };
119
120 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600121 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700122 };
123
Simon Glass5620cf82018-10-01 12:22:40 -0600124 backlight: backlight {
125 compatible = "pwm-backlight";
126 enable-gpios = <&gpio_a 1>;
127 power-supply = <&ldo_1>;
128 pwms = <&pwm 0 1000>;
129 default-brightness-level = <5>;
130 brightness-levels = <0 16 32 64 128 170 202 234 255>;
131 };
132
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200133 bind-test {
134 bind-test-child1 {
135 compatible = "sandbox,phy";
136 #phy-cells = <1>;
137 };
138
139 bind-test-child2 {
140 compatible = "simple-bus";
141 };
142 };
143
Simon Glassb2c1cac2014-02-26 15:59:21 -0700144 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600145 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700146 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600147 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700148 ping-add = <3>;
149 };
150
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200151 phy_provider0: gen_phy@0 {
152 compatible = "sandbox,phy";
153 #phy-cells = <1>;
154 };
155
156 phy_provider1: gen_phy@1 {
157 compatible = "sandbox,phy";
158 #phy-cells = <0>;
159 broken;
160 };
161
developer71092972020-05-02 11:35:12 +0200162 phy_provider2: gen_phy@2 {
163 compatible = "sandbox,phy";
164 #phy-cells = <0>;
165 };
166
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200167 gen_phy_user: gen_phy_user {
168 compatible = "simple-bus";
169 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
170 phy-names = "phy1", "phy2", "phy3";
171 };
172
developer71092972020-05-02 11:35:12 +0200173 gen_phy_user1: gen_phy_user1 {
174 compatible = "simple-bus";
175 phys = <&phy_provider0 0>, <&phy_provider2>;
176 phy-names = "phy1", "phy2";
177 };
178
Simon Glassb2c1cac2014-02-26 15:59:21 -0700179 some-bus {
180 #address-cells = <1>;
181 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600182 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600183 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600184 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700185 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600186 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700187 compatible = "denx,u-boot-fdt-test";
188 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600189 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700190 ping-add = <5>;
191 };
Simon Glass40717422014-07-23 06:55:18 -0600192 c-test@0 {
193 compatible = "denx,u-boot-fdt-test";
194 reg = <0>;
195 ping-expect = <6>;
196 ping-add = <6>;
197 };
198 c-test@1 {
199 compatible = "denx,u-boot-fdt-test";
200 reg = <1>;
201 ping-expect = <7>;
202 ping-add = <7>;
203 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700204 };
205
206 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600207 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600208 ping-expect = <6>;
209 ping-add = <6>;
210 compatible = "google,another-fdt-test";
211 };
212
213 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600214 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600215 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700216 ping-add = <6>;
217 compatible = "google,another-fdt-test";
218 };
219
Simon Glass0ccb0972015-01-25 08:27:05 -0700220 f-test {
221 compatible = "denx,u-boot-fdt-test";
222 };
223
224 g-test {
225 compatible = "denx,u-boot-fdt-test";
226 };
227
Bin Mengd9d24782018-10-10 22:07:01 -0700228 h-test {
229 compatible = "denx,u-boot-fdt-test1";
230 };
231
developercf8bc132020-05-02 11:35:10 +0200232 i-test {
233 compatible = "mediatek,u-boot-fdt-test";
234 #address-cells = <1>;
235 #size-cells = <0>;
236
237 subnode@0 {
238 reg = <0>;
239 };
240
241 subnode@1 {
242 reg = <1>;
243 };
244
245 subnode@2 {
246 reg = <2>;
247 };
248 };
249
Simon Glass204675c2019-12-29 21:19:25 -0700250 devres-test {
251 compatible = "denx,u-boot-devres-test";
252 };
253
Simon Glass2d67fdf2020-04-08 16:57:34 -0600254 acpi-test {
255 compatible = "denx,u-boot-acpi-test";
256 };
257
Simon Glass17968c32020-04-26 09:19:46 -0600258 acpi-test2 {
259 compatible = "denx,u-boot-acpi-test";
260 };
261
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200262 clocks {
263 clk_fixed: clk-fixed {
264 compatible = "fixed-clock";
265 #clock-cells = <0>;
266 clock-frequency = <1234>;
267 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000268
269 clk_fixed_factor: clk-fixed-factor {
270 compatible = "fixed-factor-clock";
271 #clock-cells = <0>;
272 clock-div = <3>;
273 clock-mult = <2>;
274 clocks = <&clk_fixed>;
275 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200276
277 osc {
278 compatible = "fixed-clock";
279 #clock-cells = <0>;
280 clock-frequency = <20000000>;
281 };
Stephen Warrena9622432016-06-17 09:44:00 -0600282 };
283
284 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600285 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600286 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200287 assigned-clocks = <&clk_sandbox 3>;
288 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600289 };
290
291 clk-test {
292 compatible = "sandbox,clk-test";
293 clocks = <&clk_fixed>,
294 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200295 <&clk_sandbox 0>,
296 <&clk_sandbox 3>,
297 <&clk_sandbox 2>;
298 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600299 };
300
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200301 ccf: clk-ccf {
302 compatible = "sandbox,clk-ccf";
303 };
304
Simon Glass5b968632015-05-22 15:42:15 -0600305 eth@10002000 {
306 compatible = "sandbox,eth";
307 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500308 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600309 };
310
311 eth_5: eth@10003000 {
312 compatible = "sandbox,eth";
313 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500314 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600315 };
316
Bin Meng04a11cb2015-08-27 22:25:53 -0700317 eth_3: sbe5 {
318 compatible = "sandbox,eth";
319 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500320 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700321 };
322
Simon Glass5b968632015-05-22 15:42:15 -0600323 eth@10004000 {
324 compatible = "sandbox,eth";
325 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500326 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600327 };
328
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700329 firmware {
330 sandbox_firmware: sandbox-firmware {
331 compatible = "sandbox,firmware";
332 };
333 };
334
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100335 pinctrl-gpio {
336 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700337
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100338 gpio_a: base-gpios {
339 compatible = "sandbox,gpio";
340 gpio-controller;
341 #gpio-cells = <1>;
342 gpio-bank-name = "a";
343 sandbox,gpio-count = <20>;
344 };
345
346 gpio_b: extra-gpios {
347 compatible = "sandbox,gpio";
348 gpio-controller;
349 #gpio-cells = <5>;
350 gpio-bank-name = "b";
351 sandbox,gpio-count = <10>;
352 };
Simon Glass25348a42014-10-13 23:42:11 -0600353
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100354 gpio_c: pinmux-gpios {
355 compatible = "sandbox,gpio";
356 gpio-controller;
357 #gpio-cells = <2>;
358 gpio-bank-name = "c";
359 sandbox,gpio-count = <10>;
360 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100361 };
362
Simon Glass7df766e2014-12-10 08:55:55 -0700363 i2c@0 {
364 #address-cells = <1>;
365 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600366 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700367 compatible = "sandbox,i2c";
368 clock-frequency = <100000>;
369 eeprom@2c {
370 reg = <0x2c>;
371 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700372 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700373 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200374
Simon Glass336b2952015-05-22 15:42:17 -0600375 rtc_0: rtc@43 {
376 reg = <0x43>;
377 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700378 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600379 };
380
381 rtc_1: rtc@61 {
382 reg = <0x61>;
383 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700384 sandbox,emul = <&emul1>;
385 };
386
387 i2c_emul: emul {
388 reg = <0xff>;
389 compatible = "sandbox,i2c-emul-parent";
390 emul_eeprom: emul-eeprom {
391 compatible = "sandbox,i2c-eeprom";
392 sandbox,filename = "i2c.bin";
393 sandbox,size = <256>;
394 };
395 emul0: emul0 {
396 compatible = "sandbox,i2c-rtc";
397 };
398 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600399 compatible = "sandbox,i2c-rtc";
400 };
401 };
402
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200403 sandbox_pmic: sandbox_pmic {
404 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700405 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200406 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200407
408 mc34708: pmic@41 {
409 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700410 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200411 };
Simon Glass7df766e2014-12-10 08:55:55 -0700412 };
413
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100414 bootcount@0 {
415 compatible = "u-boot,bootcount-rtc";
416 rtc = <&rtc_1>;
417 offset = <0x13>;
418 };
419
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100420 adc@0 {
421 compatible = "sandbox,adc";
422 vdd-supply = <&buck2>;
423 vss-microvolts = <0>;
424 };
425
Simon Glass515dcff2020-02-06 09:55:00 -0700426 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700427 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700428 interrupt-controller;
429 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700430 };
431
Simon Glass90b6fef2016-01-18 19:52:26 -0700432 lcd {
433 u-boot,dm-pre-reloc;
434 compatible = "sandbox,lcd-sdl";
435 xres = <1366>;
436 yres = <768>;
437 };
438
Simon Glassd783eb32015-07-06 12:54:34 -0600439 leds {
440 compatible = "gpio-leds";
441
442 iracibble {
443 gpios = <&gpio_a 1 0>;
444 label = "sandbox:red";
445 };
446
447 martinet {
448 gpios = <&gpio_a 2 0>;
449 label = "sandbox:green";
450 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200451
452 default_on {
453 gpios = <&gpio_a 5 0>;
454 label = "sandbox:default_on";
455 default-state = "on";
456 };
457
458 default_off {
459 gpios = <&gpio_a 6 0>;
460 label = "sandbox:default_off";
461 default-state = "off";
462 };
Simon Glassd783eb32015-07-06 12:54:34 -0600463 };
464
Stephen Warren62f2c902016-05-16 17:41:37 -0600465 mbox: mbox {
466 compatible = "sandbox,mbox";
467 #mbox-cells = <1>;
468 };
469
470 mbox-test {
471 compatible = "sandbox,mbox-test";
472 mboxes = <&mbox 100>, <&mbox 1>;
473 mbox-names = "other", "test";
474 };
475
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900476 cpus {
477 cpu-test1 {
478 compatible = "sandbox,cpu_sandbox";
479 u-boot,dm-pre-reloc;
480 };
Mario Sixdea5df72018-08-06 10:23:44 +0200481
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900482 cpu-test2 {
483 compatible = "sandbox,cpu_sandbox";
484 u-boot,dm-pre-reloc;
485 };
Mario Sixdea5df72018-08-06 10:23:44 +0200486
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900487 cpu-test3 {
488 compatible = "sandbox,cpu_sandbox";
489 u-boot,dm-pre-reloc;
490 };
Mario Sixdea5df72018-08-06 10:23:44 +0200491 };
492
Simon Glassc953aaf2018-12-10 10:37:34 -0700493 i2s: i2s {
494 compatible = "sandbox,i2s";
495 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700496 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700497 };
498
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200499 nop-test_0 {
500 compatible = "sandbox,nop_sandbox1";
501 nop-test_1 {
502 compatible = "sandbox,nop_sandbox2";
503 bind = "True";
504 };
505 nop-test_2 {
506 compatible = "sandbox,nop_sandbox2";
507 bind = "False";
508 };
509 };
510
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200511 misc-test {
512 compatible = "sandbox,misc_sandbox";
513 };
514
Simon Glasse4fef742017-04-23 20:02:07 -0600515 mmc2 {
516 compatible = "sandbox,mmc";
517 };
518
519 mmc1 {
520 compatible = "sandbox,mmc";
521 };
522
523 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600524 compatible = "sandbox,mmc";
525 };
526
Simon Glass53a68b32019-02-16 20:24:50 -0700527 pch {
528 compatible = "sandbox,pch";
529 };
530
Tom Rini4a3ca482020-02-11 12:41:23 -0500531 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700532 compatible = "sandbox,pci";
533 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500534 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700535 #address-cells = <3>;
536 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600537 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700538 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700539 pci@0,0 {
540 compatible = "pci-generic";
541 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600542 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700543 };
Alex Margineanf1274432019-06-07 11:24:24 +0300544 pci@1,0 {
545 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600546 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
547 reg = <0x02000814 0 0 0 0
548 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600549 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300550 };
Simon Glass937bb472019-12-06 21:41:57 -0700551 p2sb-pci@2,0 {
552 compatible = "sandbox,p2sb";
553 reg = <0x02001010 0 0 0 0>;
554 sandbox,emul = <&p2sb_emul>;
555
556 adder {
557 intel,p2sb-port-id = <3>;
558 compatible = "sandbox,adder";
559 };
560 };
Simon Glass8c501022019-12-06 21:41:54 -0700561 pci@1e,0 {
562 compatible = "sandbox,pmc";
563 reg = <0xf000 0 0 0 0>;
564 sandbox,emul = <&pmc_emul1e>;
565 acpi-base = <0x400>;
566 gpe0-dwx-mask = <0xf>;
567 gpe0-dwx-shift-base = <4>;
568 gpe0-dw = <6 7 9>;
569 gpe0-sts = <0x20>;
570 gpe0-en = <0x30>;
571 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700572 pci@1f,0 {
573 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600574 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
575 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600576 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700577 };
578 };
579
Simon Glassb98ba4c2019-09-25 08:56:10 -0600580 pci-emul0 {
581 compatible = "sandbox,pci-emul-parent";
582 swap_case_emul0_0: emul0@0,0 {
583 compatible = "sandbox,swap-case";
584 };
585 swap_case_emul0_1: emul0@1,0 {
586 compatible = "sandbox,swap-case";
587 use-ea;
588 };
589 swap_case_emul0_1f: emul0@1f,0 {
590 compatible = "sandbox,swap-case";
591 };
Simon Glass937bb472019-12-06 21:41:57 -0700592 p2sb_emul: emul@2,0 {
593 compatible = "sandbox,p2sb-emul";
594 };
Simon Glass8c501022019-12-06 21:41:54 -0700595 pmc_emul1e: emul@1e,0 {
596 compatible = "sandbox,pmc-emul";
597 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600598 };
599
Tom Rini4a3ca482020-02-11 12:41:23 -0500600 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700601 compatible = "sandbox,pci";
602 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500603 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700604 #address-cells = <3>;
605 #size-cells = <2>;
606 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
607 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700608 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200609 0x0c 0x00 0x1234 0x5678
610 0x10 0x00 0x1234 0x5678>;
611 pci@10,0 {
612 reg = <0x8000 0 0 0 0>;
613 };
Bin Meng408e5902018-08-03 01:14:41 -0700614 };
615
Tom Rini4a3ca482020-02-11 12:41:23 -0500616 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700617 compatible = "sandbox,pci";
618 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500619 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700620 #address-cells = <3>;
621 #size-cells = <2>;
622 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
623 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
624 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
625 pci@1f,0 {
626 compatible = "pci-generic";
627 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600628 sandbox,emul = <&swap_case_emul2_1f>;
629 };
630 };
631
632 pci-emul2 {
633 compatible = "sandbox,pci-emul-parent";
634 swap_case_emul2_1f: emul2@1f,0 {
635 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700636 };
637 };
638
Ramon Friedc64f19b2019-04-27 11:15:23 +0300639 pci_ep: pci_ep {
640 compatible = "sandbox,pci_ep";
641 };
642
Simon Glass9c433fe2017-04-23 20:10:44 -0600643 probing {
644 compatible = "simple-bus";
645 test1 {
646 compatible = "denx,u-boot-probe-test";
647 };
648
649 test2 {
650 compatible = "denx,u-boot-probe-test";
651 };
652
653 test3 {
654 compatible = "denx,u-boot-probe-test";
655 };
656
657 test4 {
658 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100659 first-syscon = <&syscon0>;
660 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100661 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600662 };
663 };
664
Stephen Warren92c67fa2016-07-13 13:45:31 -0600665 pwrdom: power-domain {
666 compatible = "sandbox,power-domain";
667 #power-domain-cells = <1>;
668 };
669
670 power-domain-test {
671 compatible = "sandbox,power-domain-test";
672 power-domains = <&pwrdom 2>;
673 };
674
Simon Glass5620cf82018-10-01 12:22:40 -0600675 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600676 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600677 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600678 };
679
680 pwm2 {
681 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600682 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600683 };
684
Simon Glass3d355e62015-07-06 12:54:31 -0600685 ram {
686 compatible = "sandbox,ram";
687 };
688
Simon Glassd860f222015-07-06 12:54:29 -0600689 reset@0 {
690 compatible = "sandbox,warm-reset";
691 };
692
693 reset@1 {
694 compatible = "sandbox,reset";
695 };
696
Stephen Warren6488e642016-06-17 09:43:59 -0600697 resetc: reset-ctl {
698 compatible = "sandbox,reset-ctl";
699 #reset-cells = <1>;
700 };
701
702 reset-ctl-test {
703 compatible = "sandbox,reset-ctl-test";
704 resets = <&resetc 100>, <&resetc 2>;
705 reset-names = "other", "test";
706 };
707
Sughosh Ganu23e37512019-12-28 23:58:31 +0530708 rng {
709 compatible = "sandbox,sandbox-rng";
710 };
711
Nishanth Menonedf85812015-09-17 15:42:41 -0500712 rproc_1: rproc@1 {
713 compatible = "sandbox,test-processor";
714 remoteproc-name = "remoteproc-test-dev1";
715 };
716
717 rproc_2: rproc@2 {
718 compatible = "sandbox,test-processor";
719 internal-memory-mapped;
720 remoteproc-name = "remoteproc-test-dev2";
721 };
722
Simon Glass5620cf82018-10-01 12:22:40 -0600723 panel {
724 compatible = "simple-panel";
725 backlight = <&backlight 0 100>;
726 };
727
Ramon Fried26ed32e2018-07-02 02:57:59 +0300728 smem@0 {
729 compatible = "sandbox,smem";
730 };
731
Simon Glass76072ac2018-12-10 10:37:36 -0700732 sound {
733 compatible = "sandbox,sound";
734 cpu {
735 sound-dai = <&i2s 0>;
736 };
737
738 codec {
739 sound-dai = <&audio 0>;
740 };
741 };
742
Simon Glass25348a42014-10-13 23:42:11 -0600743 spi@0 {
744 #address-cells = <1>;
745 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600746 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600747 compatible = "sandbox,spi";
748 cs-gpios = <0>, <&gpio_a 0>;
749 spi.bin@0 {
750 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000751 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600752 spi-max-frequency = <40000000>;
753 sandbox,filename = "spi.bin";
754 };
755 };
756
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100757 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600758 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200759 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600760 };
761
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100762 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600763 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600764 reg = <0x20 5
765 0x28 6
766 0x30 7
767 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600768 };
769
Patrick Delaunayee010432019-03-07 09:57:13 +0100770 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900771 compatible = "simple-mfd", "syscon";
772 reg = <0x40 5
773 0x48 6
774 0x50 7
775 0x58 8>;
776 };
777
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800778 timer {
779 compatible = "sandbox,timer";
780 clock-frequency = <1000000>;
781 };
782
Miquel Raynal80938c12018-05-15 11:57:27 +0200783 tpm2 {
784 compatible = "sandbox,tpm2";
785 };
786
Simon Glass5b968632015-05-22 15:42:15 -0600787 uart0: serial {
788 compatible = "sandbox,serial";
789 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500790 };
791
Simon Glass31680482015-03-25 12:23:05 -0600792 usb_0: usb@0 {
793 compatible = "sandbox,usb";
794 status = "disabled";
795 hub {
796 compatible = "sandbox,usb-hub";
797 #address-cells = <1>;
798 #size-cells = <0>;
799 flash-stick {
800 reg = <0>;
801 compatible = "sandbox,usb-flash";
802 };
803 };
804 };
805
806 usb_1: usb@1 {
807 compatible = "sandbox,usb";
808 hub {
809 compatible = "usb-hub";
810 usb,device-class = <9>;
811 hub-emul {
812 compatible = "sandbox,usb-hub";
813 #address-cells = <1>;
814 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700815 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600816 reg = <0>;
817 compatible = "sandbox,usb-flash";
818 sandbox,filepath = "testflash.bin";
819 };
820
Simon Glass4700fe52015-11-08 23:48:01 -0700821 flash-stick@1 {
822 reg = <1>;
823 compatible = "sandbox,usb-flash";
824 sandbox,filepath = "testflash1.bin";
825 };
826
827 flash-stick@2 {
828 reg = <2>;
829 compatible = "sandbox,usb-flash";
830 sandbox,filepath = "testflash2.bin";
831 };
832
Simon Glassc0ccc722015-11-08 23:48:08 -0700833 keyb@3 {
834 reg = <3>;
835 compatible = "sandbox,usb-keyb";
836 };
837
Simon Glass31680482015-03-25 12:23:05 -0600838 };
839 };
840 };
841
842 usb_2: usb@2 {
843 compatible = "sandbox,usb";
844 status = "disabled";
845 };
846
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200847 spmi: spmi@0 {
848 compatible = "sandbox,spmi";
849 #address-cells = <0x1>;
850 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600851 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200852 pm8916@0 {
853 compatible = "qcom,spmi-pmic";
854 reg = <0x0 0x1>;
855 #address-cells = <0x1>;
856 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600857 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200858
859 spmi_gpios: gpios@c000 {
860 compatible = "qcom,pm8916-gpio";
861 reg = <0xc000 0x400>;
862 gpio-controller;
863 gpio-count = <4>;
864 #gpio-cells = <2>;
865 gpio-bank-name="spmi";
866 };
867 };
868 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700869
870 wdt0: wdt@0 {
871 compatible = "sandbox,wdt";
872 };
Rob Clarka471b672018-01-10 11:33:30 +0100873
Mario Six95922152018-08-09 14:51:19 +0200874 axi: axi@0 {
875 compatible = "sandbox,axi";
876 #address-cells = <0x1>;
877 #size-cells = <0x1>;
878 store@0 {
879 compatible = "sandbox,sandbox_store";
880 reg = <0x0 0x400>;
881 };
882 };
883
Rob Clarka471b672018-01-10 11:33:30 +0100884 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700885 #address-cells = <1>;
886 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -0700887 setting = "sunrise ohoka";
888 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -0700889 int-values = <0x1937 72993>;
Rob Clarka471b672018-01-10 11:33:30 +0100890 chosen-test {
891 compatible = "denx,u-boot-fdt-test";
892 reg = <9 1>;
893 };
894 };
Mario Six35616ef2018-03-12 14:53:33 +0100895
896 translation-test@8000 {
897 compatible = "simple-bus";
898 reg = <0x8000 0x4000>;
899
900 #address-cells = <0x2>;
901 #size-cells = <0x1>;
902
903 ranges = <0 0x0 0x8000 0x1000
904 1 0x100 0x9000 0x1000
905 2 0x200 0xA000 0x1000
906 3 0x300 0xB000 0x1000
907 >;
908
Fabien Dessenne22236e02019-05-31 15:11:30 +0200909 dma-ranges = <0 0x000 0x10000000 0x1000
910 1 0x100 0x20000000 0x1000
911 >;
912
Mario Six35616ef2018-03-12 14:53:33 +0100913 dev@0,0 {
914 compatible = "denx,u-boot-fdt-dummy";
915 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100916 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100917 };
918
919 dev@1,100 {
920 compatible = "denx,u-boot-fdt-dummy";
921 reg = <1 0x100 0x1000>;
922
923 };
924
925 dev@2,200 {
926 compatible = "denx,u-boot-fdt-dummy";
927 reg = <2 0x200 0x1000>;
928 };
929
930
931 noxlatebus@3,300 {
932 compatible = "simple-bus";
933 reg = <3 0x300 0x1000>;
934
935 #address-cells = <0x1>;
936 #size-cells = <0x0>;
937
938 dev@42 {
939 compatible = "denx,u-boot-fdt-dummy";
940 reg = <0x42>;
941 };
942 };
943 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200944
945 osd {
946 compatible = "sandbox,sandbox_osd";
947 };
Tom Rinib93eea72018-09-30 18:16:51 -0400948
Mario Sixab664ff2018-07-31 11:44:13 +0200949 board {
950 compatible = "sandbox,board_sandbox";
951 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200952
953 sandbox_tee {
954 compatible = "sandbox,tee";
955 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700956
957 sandbox_virtio1 {
958 compatible = "sandbox,virtio1";
959 };
960
961 sandbox_virtio2 {
962 compatible = "sandbox,virtio2";
963 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200964
965 pinctrl {
966 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +0100967
968 pinctrl-names = "default";
969 pinctrl-0 = <&gpios>;
970
971 gpios: gpios {
972 gpio0 {
973 pins = "GPIO0";
974 bias-pull-up;
975 input-disable;
976 };
977 gpio1 {
978 pins = "GPIO1";
979 output-high;
980 drive-open-drain;
981 };
982 gpio2 {
983 pins = "GPIO2";
984 bias-pull-down;
985 input-enable;
986 };
987 gpio3 {
988 pins = "GPIO3";
989 bias-disable;
990 };
991 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200992 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +0100993
994 hwspinlock@0 {
995 compatible = "sandbox,hwspinlock";
996 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100997
998 dma: dma {
999 compatible = "sandbox,dma";
1000 #dma-cells = <1>;
1001
1002 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1003 dma-names = "m2m", "tx0", "rx0";
1004 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001005
Alex Marginean0649be52019-07-12 10:13:53 +03001006 /*
1007 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1008 * end of the test. If parent mdio is removed first, clean-up of the
1009 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1010 * active at the end of the test. That it turn doesn't allow the mdio
1011 * class to be destroyed, triggering an error.
1012 */
1013 mdio-mux-test {
1014 compatible = "sandbox,mdio-mux";
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017 mdio-parent-bus = <&mdio>;
1018
1019 mdio-ch-test@0 {
1020 reg = <0>;
1021 };
1022 mdio-ch-test@1 {
1023 reg = <1>;
1024 };
1025 };
1026
1027 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001028 compatible = "sandbox,mdio";
1029 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001030};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001031
1032#include "sandbox_pmic.dtsi"