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git01.mediatek.com / filogic / uboot / abe667df89f185b26843be375744bc3dcbf56fe4 / . / arch / arm / dts / rk3399-rock-4c-plus-u-boot.dtsi
blob: 7a6af430a6f4ec7cebbc73506904ae15dfc475b2 [file] [log] [blame]
FUKAUMI Naoki7fe97a72024-08-16 07:37:13 +0900[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
FUKAUMI Naokifc517a72023-04-26 02:23:54 +0000[diff] [blame]2/*
FUKAUMI Naoki7fe97a72024-08-16 07:37:13 +0900[diff] [blame]3 * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
FUKAUMI Naokifc517a72023-04-26 02:23:54 +0000[diff] [blame]4 * Copyright (c) 2023 Radxa Limited
5 */
FUKAUMI Naoki7fe97a72024-08-16 07:37:13 +0900[diff] [blame]6#include "rk3399-u-boot.dtsi"
7#include "rk3399-sdram-lpddr4-100.dtsi"
Jonas Karlman6a6b4f52024-04-30 15:30:24 +0000[diff] [blame]8
FUKAUMI Naokiabe667d2024-08-09 07:23:25 +0900[diff] [blame^]9/ {
10 leds {
11 led-0 {
12 default-state = "on";
13 };
14
15 led-1 {
16 default-state = "on";
17 };
18 };
19};
20
Jonas Karlman6a6b4f52024-04-30 15:30:24 +0000[diff] [blame]21&pcfg_pull_none_18ma {
22 bootph-pre-ram;
23 bootph-some-ram;
24};
25
26&pcfg_pull_up_8ma {
27 bootph-pre-ram;
28 bootph-some-ram;
29};
Jonas Karlman0ab86782024-05-01 16:22:35 +0000[diff] [blame]30
FUKAUMI Naoki7fe97a72024-08-16 07:37:13 +0900[diff] [blame]31&sdhci {
32 cap-mmc-highspeed;
33 mmc-ddr-1_8v;
34 mmc-hs200-1_8v;
35};
36
Jonas Karlman0ab86782024-05-01 16:22:35 +0000[diff] [blame]37&spi1 {
38 status = "okay";
39
40 flash@0 {
41 compatible = "jedec,spi-nor";
42 reg = <0>;
43 bootph-pre-ram;
44 bootph-some-ram;
45 spi-max-frequency = <10000000>;
46 };
47};
FUKAUMI Naoki7fe97a72024-08-16 07:37:13 +0900[diff] [blame]48
49&vdd_log {
50 regulator-init-microvolt = <950000>;
51};