Blame - board/esd/pci405/writeibm.S - filogic/uboot

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Wolfgang Denk	52744b4	2013-07-28 22:12:45 +0200	[diff] [blame]	1	/*
Wolfgang Denk	815c967	2013-09-17 11:24:06 +0200	[diff] [blame]	2	* SPDX-License-Identifier: GPL-2.0 IBM-pibs
Wolfgang Denk	52744b4	2013-07-28 22:12:45 +0200	[diff] [blame]	3	*/
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	4	/----------------------------------------------------------------------------- /
				5	/* Function: ext_bus_cntlr_init */
				6	/* Description: Initializes the External Bus Controller for the external */
				7	/* peripherals. IMPORTANT: For pass1 this code must run from */
				8	/* cache since you can not reliably change a peripheral banks */
				9	/* timing register (pbxap) while running code from that bank. */
				10	/* For ex., since we are running from ROM on bank 0, we can NOT */
				11	/* execute the code that modifies bank 0 timings from ROM, so */
				12	/* we run it from cache. */
				13	/* Bank 0 - Flash and SRAM */
				14	/* Bank 1 - NVRAM/RTC */
				15	/* Bank 2 - Keyboard/Mouse controller */
				16	/* Bank 3 - IR controller */
				17	/* Bank 4 - not used */
				18	/* Bank 5 - not used */
				19	/* Bank 6 - not used */
				20	/* Bank 7 - FPGA registers */
				21	/----------------------------------------------------------------------------- /
Stefan Roese	247e9d7	2010-09-09 19:18:00 +0200	[diff] [blame]	22	#include <asm/ppc4xx.h>
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	23
				24	#include <ppc_asm.tmpl>
				25	#include <ppc_defs.h>
				26
				27	#include <asm/cache.h>
				28	#include <asm/mmu.h>
				29
				30
				31	.globl write_without_sync
				32	write_without_sync:
				33	/*
				34	* Write one values to host via pci busmastering
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	35	* ptr = 0xc0000000 -> 0x01000000 (PCI)
				36	* *ptr = 0x01234567;
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	37	*/
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	38	addi r31,0,0
				39	lis r31,0xc000
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	40
				41	start1:
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	42	lis r0,0x0123
				43	ori r0,r0,0x4567
				44	stw r0,0(r31)
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	45
				46	/*
				47	* Read one value back
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	48	* ptr = (volatile unsigned long *)addr;
				49	* val = *ptr;
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	50	*/
				51
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	52	lwz r0,0(r31)
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	53
				54	/*
				55	* One pci config write
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	56	* ibmPciConfigWrite(0x2e, 2, 0x1234);
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	57	*/
				58	/* subsystem id */
				59
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	60	li r4,0x002C
				61	oris r4,r4,0x8000
				62	lis r3,0xEEC0
				63	stwbrx r4,0,r3
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	64
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	65	li r5,0x1234
				66	ori r3,r3,0x4
				67	stwbrx r5,0,r3
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	68
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	69	b start1
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	70
				71	blr /* never reached !!!! */
				72
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	73	.globl write_with_sync
				74	write_with_sync:
				75	/*
				76	* Write one values to host via pci busmastering
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	77	* ptr = 0xc0000000 -> 0x01000000 (PCI)
				78	* *ptr = 0x01234567;
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	79	*/
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	80	addi r31,0,0
				81	lis r31,0xc000
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	82
				83	start2:
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	84	lis r0,0x0123
				85	ori r0,r0,0x4567
				86	stw r0,0(r31)
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	87
				88	/*
				89	* Read one value back
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	90	* ptr = (volatile unsigned long *)addr;
				91	* val = *ptr;
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	92	*/
				93
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	94	lwz r0,0(r31)
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	95
				96	/*
				97	* One pci config write
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	98	* ibmPciConfigWrite(0x2e, 2, 0x1234);
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	99	*/
				100	/* subsystem id */
				101
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	102	li r4,0x002C
				103	oris r4,r4,0x8000
				104	lis r3,0xEEC0
				105	stwbrx r4,0,r3
				106	sync
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	107
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	108	li r5,0x1234
				109	ori r3,r3,0x4
				110	stwbrx r5,0,r3
				111	sync
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	112
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	113	b start2
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	114
				115	blr /* never reached !!!! */
				116
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	117	.globl write_with_less_sync
				118	write_with_less_sync:
				119	/*
				120	* Write one values to host via pci busmastering
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	121	* ptr = 0xc0000000 -> 0x01000000 (PCI)
				122	* *ptr = 0x01234567;
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	123	*/
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	124	addi r31,0,0
				125	lis r31,0xc000
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	126
				127	start2b:
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	128	lis r0,0x0123
				129	ori r0,r0,0x4567
				130	stw r0,0(r31)
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	131
				132	/*
				133	* Read one value back
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	134	* ptr = (volatile unsigned long *)addr;
				135	* val = *ptr;
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	136	*/
				137
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	138	lwz r0,0(r31)
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	139
				140	/*
				141	* One pci config write
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	142	* ibmPciConfigWrite(0x2e, 2, 0x1234);
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	143	*/
				144	/* subsystem id */
				145
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	146	li r4,0x002C
				147	oris r4,r4,0x8000
				148	lis r3,0xEEC0
				149	stwbrx r4,0,r3
				150	sync
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	151
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	152	li r5,0x1234
				153	ori r3,r3,0x4
				154	stwbrx r5,0,r3
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	155	/* sync */
				156
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	157	b start2b
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	158
				159	blr /* never reached !!!! */
				160
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	161	.globl write_with_more_sync
				162	write_with_more_sync:
				163	/*
				164	* Write one values to host via pci busmastering
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	165	* ptr = 0xc0000000 -> 0x01000000 (PCI)
				166	* *ptr = 0x01234567;
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	167	*/
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	168	addi r31,0,0
				169	lis r31,0xc000
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	170
				171	start3:
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	172	lis r0,0x0123
				173	ori r0,r0,0x4567
				174	stw r0,0(r31)
				175	sync
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	176
				177	/*
				178	* Read one value back
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	179	* ptr = (volatile unsigned long *)addr;
				180	* val = *ptr;
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	181	*/
				182
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	183	lwz r0,0(r31)
				184	sync
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	185
				186	/*
				187	* One pci config write
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	188	* ibmPciConfigWrite(0x2e, 2, 0x1234);
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	189	*/
				190	/* subsystem id (PCIC0_SBSYSVID)*/
				191
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	192	li r4,0x002C
				193	oris r4,r4,0x8000
				194	lis r3,0xEEC0
				195	stwbrx r4,0,r3
				196	sync
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	197
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	198	li r5,0x1234
				199	ori r3,r3,0x4
				200	stwbrx r5,0,r3
				201	sync
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	202
wdenk	07d7e6b	2004-12-16 21:44:03 +0000	[diff] [blame]	203	b start3
stroese	4848a32	2004-12-16 19:10:22 +0000	[diff] [blame]	204
				205	blr /* never reached !!!! */