Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
Gaurav Jain | 81113a0 | 2022-03-24 11:50:27 +0530 | [diff] [blame] | 3 | * Copyright 2018, 2021 NXP |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 4 | * |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Tom Rini | abb9a04 | 2024-05-18 20:20:43 -0600 | [diff] [blame^] | 7 | #include <common.h> |
Simon Glass | f11478f | 2019-12-28 10:45:07 -0700 | [diff] [blame] | 8 | #include <hang.h> |
Simon Glass | 2dc9c34 | 2020-05-10 11:40:01 -0600 | [diff] [blame] | 9 | #include <image.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 10 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 11 | #include <log.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 12 | #include <asm/global_data.h> |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 13 | #include <asm/io.h> |
| 14 | #include <errno.h> |
| 15 | #include <asm/io.h> |
| 16 | #include <asm/arch/ddr.h> |
| 17 | #include <asm/arch/imx8mq_pins.h> |
| 18 | #include <asm/arch/sys_proto.h> |
| 19 | #include <asm/arch/clock.h> |
| 20 | #include <asm/mach-imx/iomux-v3.h> |
| 21 | #include <asm/mach-imx/gpio.h> |
| 22 | #include <asm/mach-imx/mxc_i2c.h> |
Shiji Yang | bb11234 | 2023-08-03 09:47:16 +0800 | [diff] [blame] | 23 | #include <asm/sections.h> |
Yangbo Lu | 7334038 | 2019-06-21 11:42:28 +0800 | [diff] [blame] | 24 | #include <fsl_esdhc_imx.h> |
Gaurav Jain | 81113a0 | 2022-03-24 11:50:27 +0530 | [diff] [blame] | 25 | #include <fsl_sec.h> |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 26 | #include <mmc.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 27 | #include <linux/delay.h> |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 28 | #include <power/pmic.h> |
| 29 | #include <power/pfuze100_pmic.h> |
| 30 | #include <spl.h> |
| 31 | #include "../common/pfuze.h" |
| 32 | |
| 33 | DECLARE_GLOBAL_DATA_PTR; |
| 34 | |
| 35 | extern struct dram_timing_info dram_timing_b0; |
| 36 | |
Fabio Estevam | 639f101 | 2019-05-18 13:18:45 -0300 | [diff] [blame] | 37 | static void spl_dram_init(void) |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 38 | { |
| 39 | /* ddr init */ |
Ye Li | 10be3fb | 2021-03-19 15:57:18 +0800 | [diff] [blame] | 40 | if (soc_rev() >= CHIP_REV_2_1) |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 41 | ddr_init(&dram_timing); |
| 42 | else |
| 43 | ddr_init(&dram_timing_b0); |
| 44 | } |
| 45 | |
| 46 | #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) |
| 47 | #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
Fabio Estevam | 639f101 | 2019-05-18 13:18:45 -0300 | [diff] [blame] | 48 | static struct i2c_pads_info i2c_pad_info1 = { |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 49 | .scl = { |
| 50 | .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, |
| 51 | .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, |
| 52 | .gp = IMX_GPIO_NR(5, 14), |
| 53 | }, |
| 54 | .sda = { |
| 55 | .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, |
| 56 | .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, |
| 57 | .gp = IMX_GPIO_NR(5, 15), |
| 58 | }, |
| 59 | }; |
| 60 | |
| 61 | #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) |
| 62 | #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) |
| 63 | #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) |
| 64 | |
| 65 | int board_mmc_getcd(struct mmc *mmc) |
| 66 | { |
| 67 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 68 | int ret = 0; |
| 69 | |
| 70 | switch (cfg->esdhc_base) { |
| 71 | case USDHC1_BASE_ADDR: |
| 72 | ret = 1; |
| 73 | break; |
| 74 | case USDHC2_BASE_ADDR: |
| 75 | ret = !gpio_get_value(USDHC2_CD_GPIO); |
| 76 | return ret; |
| 77 | } |
| 78 | |
| 79 | return 1; |
| 80 | } |
| 81 | |
| 82 | #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ |
| 83 | PAD_CTL_FSEL2) |
| 84 | #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) |
| 85 | |
| 86 | static iomux_v3_cfg_t const usdhc1_pads[] = { |
| 87 | IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 88 | IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 89 | IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 90 | IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 91 | IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 92 | IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 93 | IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 94 | IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 95 | IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 96 | IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 97 | IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 98 | }; |
| 99 | |
| 100 | static iomux_v3_cfg_t const usdhc2_pads[] = { |
| 101 | IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
| 102 | IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
| 103 | IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
| 104 | IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
| 105 | IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ |
| 106 | IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ |
| 107 | IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), |
| 108 | IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), |
| 109 | }; |
| 110 | |
| 111 | static struct fsl_esdhc_cfg usdhc_cfg[2] = { |
| 112 | {USDHC1_BASE_ADDR, 0, 8}, |
| 113 | {USDHC2_BASE_ADDR, 0, 4}, |
| 114 | }; |
| 115 | |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 116 | int board_mmc_init(struct bd_info *bis) |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 117 | { |
| 118 | int i, ret; |
| 119 | /* |
| 120 | * According to the board_mmc_init() the following map is done: |
| 121 | * (U-Boot device node) (Physical Port) |
| 122 | * mmc0 USDHC1 |
| 123 | * mmc1 USDHC2 |
| 124 | */ |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 125 | for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 126 | switch (i) { |
| 127 | case 0: |
| 128 | init_clk_usdhc(0); |
| 129 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); |
| 130 | imx_iomux_v3_setup_multiple_pads(usdhc1_pads, |
| 131 | ARRAY_SIZE(usdhc1_pads)); |
| 132 | gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); |
| 133 | gpio_direction_output(USDHC1_PWR_GPIO, 0); |
| 134 | udelay(500); |
| 135 | gpio_direction_output(USDHC1_PWR_GPIO, 1); |
| 136 | break; |
| 137 | case 1: |
| 138 | init_clk_usdhc(1); |
| 139 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); |
| 140 | imx_iomux_v3_setup_multiple_pads(usdhc2_pads, |
| 141 | ARRAY_SIZE(usdhc2_pads)); |
| 142 | gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); |
| 143 | gpio_direction_output(USDHC2_PWR_GPIO, 0); |
| 144 | udelay(500); |
| 145 | gpio_direction_output(USDHC2_PWR_GPIO, 1); |
| 146 | break; |
| 147 | default: |
| 148 | printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); |
| 149 | return -EINVAL; |
| 150 | } |
| 151 | |
| 152 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| 153 | if (ret) |
| 154 | return ret; |
| 155 | } |
| 156 | |
| 157 | return 0; |
| 158 | } |
| 159 | |
Simon Glass | 3133941 | 2021-08-08 12:20:27 -0600 | [diff] [blame] | 160 | #if CONFIG_IS_ENABLED(POWER_LEGACY) |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 161 | #define I2C_PMIC 0 |
| 162 | int power_init_board(void) |
| 163 | { |
| 164 | struct pmic *p; |
| 165 | int ret; |
| 166 | unsigned int reg; |
| 167 | |
| 168 | ret = power_pfuze100_init(I2C_PMIC); |
| 169 | if (ret) |
| 170 | return -ENODEV; |
| 171 | |
| 172 | p = pmic_get("PFUZE100"); |
| 173 | ret = pmic_probe(p); |
| 174 | if (ret) |
| 175 | return -ENODEV; |
| 176 | |
| 177 | pmic_reg_read(p, PFUZE100_DEVICEID, ®); |
| 178 | printf("PMIC: PFUZE100 ID=0x%02x\n", reg); |
| 179 | |
| 180 | pmic_reg_read(p, PFUZE100_SW3AVOL, ®); |
| 181 | if ((reg & 0x3f) != 0x18) { |
| 182 | reg &= ~0x3f; |
| 183 | reg |= 0x18; |
| 184 | pmic_reg_write(p, PFUZE100_SW3AVOL, reg); |
| 185 | } |
| 186 | |
| 187 | ret = pfuze_mode_init(p, APS_PFM); |
| 188 | if (ret < 0) |
| 189 | return ret; |
| 190 | |
| 191 | /* set SW3A standby mode to off */ |
| 192 | pmic_reg_read(p, PFUZE100_SW3AMODE, ®); |
| 193 | reg &= ~0xf; |
| 194 | reg |= APS_OFF; |
| 195 | pmic_reg_write(p, PFUZE100_SW3AMODE, reg); |
| 196 | |
| 197 | return 0; |
| 198 | } |
| 199 | #endif |
| 200 | |
| 201 | void spl_board_init(void) |
| 202 | { |
Gaurav Jain | 81113a0 | 2022-03-24 11:50:27 +0530 | [diff] [blame] | 203 | if (IS_ENABLED(CONFIG_FSL_CAAM)) { |
| 204 | if (sec_init()) |
| 205 | printf("\nsec_init failed!\n"); |
| 206 | } |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 207 | puts("Normal Boot\n"); |
| 208 | } |
| 209 | |
| 210 | #ifdef CONFIG_SPL_LOAD_FIT |
| 211 | int board_fit_config_name_match(const char *name) |
| 212 | { |
| 213 | /* Just empty function now - can't decide what to choose */ |
| 214 | debug("%s: %s\n", __func__, name); |
| 215 | |
| 216 | return 0; |
| 217 | } |
| 218 | #endif |
| 219 | |
| 220 | void board_init_f(ulong dummy) |
| 221 | { |
| 222 | int ret; |
| 223 | |
| 224 | /* Clear global data */ |
| 225 | memset((void *)gd, 0, sizeof(gd_t)); |
| 226 | |
| 227 | arch_cpu_init(); |
| 228 | |
| 229 | init_uart_clk(0); |
| 230 | |
| 231 | board_early_init_f(); |
| 232 | |
| 233 | timer_init(); |
| 234 | |
| 235 | preloader_console_init(); |
| 236 | |
| 237 | /* Clear the BSS. */ |
| 238 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 239 | |
| 240 | ret = spl_init(); |
| 241 | if (ret) { |
| 242 | debug("spl_init() failed: %d\n", ret); |
| 243 | hang(); |
| 244 | } |
| 245 | |
| 246 | enable_tzc380(); |
| 247 | |
Peng Fan | aeb9c06 | 2018-11-20 10:20:00 +0000 | [diff] [blame] | 248 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
| 249 | |
| 250 | power_init_board(); |
| 251 | |
| 252 | /* DDR initialization */ |
| 253 | spl_dram_init(); |
| 254 | |
| 255 | board_init_r(NULL, 0); |
| 256 | } |