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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk324f6cf2002-10-07 21:13:39 +00002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk324f6cf2002-10-07 21:13:39 +00005 */
6
Tom Rini150c3bc2024-04-27 08:11:06 -06007#include <config.h>
8#include <linux/kernel.h>
wdenk324f6cf2002-10-07 21:13:39 +00009
wdenk324f6cf2002-10-07 21:13:39 +000010#include <post.h>
11
Yuri Tikhonovc3655b82008-05-08 15:42:47 +020012extern int ocm_post_test (int flags);
wdenk324f6cf2002-10-07 21:13:39 +000013extern int cache_post_test (int flags);
14extern int watchdog_post_test (int flags);
15extern int i2c_post_test (int flags);
16extern int rtc_post_test (int flags);
17extern int memory_post_test (int flags);
18extern int cpu_post_test (int flags);
Igor Lisitsin95bcd382007-03-28 19:06:19 +040019extern int fpu_post_test (int flags);
wdenk324f6cf2002-10-07 21:13:39 +000020extern int uart_post_test (int flags);
21extern int ether_post_test (int flags);
22extern int spi_post_test (int flags);
23extern int usb_post_test (int flags);
24extern int spr_post_test (int flags);
wdenkc08f1582003-04-27 22:52:51 +000025extern int sysmon_post_test (int flags);
wdenk61642172004-04-15 21:16:42 +000026extern int dsp_post_test (int flags);
wdenkc4e854f2004-06-07 23:46:25 +000027extern int codec_post_test (int flags);
Pavel Kolesnikov5d896112007-07-20 15:03:03 +020028extern int ecc_post_test (int flags);
Mike Frysinger813531f2011-05-10 13:35:40 +000029extern int flash_post_test(int flags);
wdenkc08f1582003-04-27 22:52:51 +000030
Yuri Tikhonovc147d482008-02-04 14:10:42 +010031extern int dspic_init_post_test (int flags);
32extern int dspic_post_test (int flags);
33extern int gdc_post_test (int flags);
34extern int fpga_post_test (int flags);
35extern int lwmon5_watchdog_post_test(int flags);
36extern int sysmon1_post_test(int flags);
Anatolij Gustschin810b2072010-04-24 19:27:11 +020037extern int coprocessor_post_test(int flags);
Mike Frysinger32ed1fe2011-05-10 16:22:25 -040038extern int led_post_test(int flags);
39extern int button_post_test(int flags);
Valentin Longchamp24db42a2011-09-12 04:18:40 +000040extern int memory_regions_post_test(int flags);
Yuri Tikhonovc147d482008-02-04 14:10:42 +010041
wdenkc08f1582003-04-27 22:52:51 +000042extern int sysmon_init_f (void);
43
44extern void sysmon_reloc (void);
45
wdenk324f6cf2002-10-07 21:13:39 +000046
47struct post_test post_list[] =
48{
Tom Rini3dd5d4a2022-12-04 10:14:17 -050049#if CFG_POST & CFG_SYS_POST_OCM
Yuri Tikhonovc3655b82008-05-08 15:42:47 +020050 {
51 "OCM test",
52 "ocm",
53 "This test checks on chip memory (OCM).",
Yuri Tikhonov9c667bf2008-05-08 15:46:02 +020054 POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL | POST_STOP,
Yuri Tikhonovc3655b82008-05-08 15:42:47 +020055 &ocm_post_test,
56 NULL,
57 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -050058 CFG_SYS_POST_OCM
Yuri Tikhonovc3655b82008-05-08 15:42:47 +020059 },
60#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -050061#if CFG_POST & CFG_SYS_POST_CACHE
wdenk324f6cf2002-10-07 21:13:39 +000062 {
wdenk57b2d802003-06-27 21:31:46 +000063 "Cache test",
64 "cache",
65 "This test verifies the CPU cache operation.",
66 POST_RAM | POST_ALWAYS,
67 &cache_post_test,
68 NULL,
69 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -050070 CFG_SYS_POST_CACHE
wdenk324f6cf2002-10-07 21:13:39 +000071 },
72#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -050073#if CFG_POST & CFG_SYS_POST_WATCHDOG
Tom Rini8eaa3c72022-11-19 18:45:44 -050074#if defined(CFG_POST_WATCHDOG)
75 CFG_POST_WATCHDOG,
Yuri Tikhonovc147d482008-02-04 14:10:42 +010076#else
wdenk324f6cf2002-10-07 21:13:39 +000077 {
wdenk57b2d802003-06-27 21:31:46 +000078 "Watchdog timer test",
79 "watchdog",
80 "This test checks the watchdog timer.",
wdenkdccbda02003-07-14 22:13:32 +000081 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT,
wdenk57b2d802003-06-27 21:31:46 +000082 &watchdog_post_test,
83 NULL,
84 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -050085 CFG_SYS_POST_WATCHDOG
wdenk324f6cf2002-10-07 21:13:39 +000086 },
87#endif
Yuri Tikhonovc147d482008-02-04 14:10:42 +010088#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -050089#if CFG_POST & CFG_SYS_POST_I2C
wdenk324f6cf2002-10-07 21:13:39 +000090 {
wdenk57b2d802003-06-27 21:31:46 +000091 "I2C test",
92 "i2c",
93 "This test verifies the I2C operation.",
94 POST_RAM | POST_ALWAYS,
95 &i2c_post_test,
96 NULL,
97 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -050098 CFG_SYS_POST_I2C
wdenk324f6cf2002-10-07 21:13:39 +000099 },
100#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500101#if CFG_POST & CFG_SYS_POST_RTC
wdenk324f6cf2002-10-07 21:13:39 +0000102 {
wdenk57b2d802003-06-27 21:31:46 +0000103 "RTC test",
104 "rtc",
105 "This test verifies the RTC operation.",
wdenkdccbda02003-07-14 22:13:32 +0000106 POST_RAM | POST_SLOWTEST | POST_MANUAL,
wdenk57b2d802003-06-27 21:31:46 +0000107 &rtc_post_test,
108 NULL,
109 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500110 CFG_SYS_POST_RTC
wdenk324f6cf2002-10-07 21:13:39 +0000111 },
112#endif
Tom Rini8eaa3c72022-11-19 18:45:44 -0500113#if CFG_POST & CFG_SYS_POST_MEMORY
wdenk324f6cf2002-10-07 21:13:39 +0000114 {
wdenk57b2d802003-06-27 21:31:46 +0000115 "Memory test",
116 "memory",
117 "This test checks RAM.",
wdenkdccbda02003-07-14 22:13:32 +0000118 POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL,
wdenk57b2d802003-06-27 21:31:46 +0000119 &memory_post_test,
120 NULL,
121 NULL,
Tom Rini6a5dccc2022-11-16 13:10:41 -0500122 CFG_SYS_POST_MEMORY
wdenk324f6cf2002-10-07 21:13:39 +0000123 },
124#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500125#if CFG_POST & CFG_SYS_POST_CPU
wdenk324f6cf2002-10-07 21:13:39 +0000126 {
wdenk57b2d802003-06-27 21:31:46 +0000127 "CPU test",
128 "cpu",
129 "This test verifies the arithmetic logic unit of"
130 " CPU.",
131 POST_RAM | POST_ALWAYS,
132 &cpu_post_test,
133 NULL,
134 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500135 CFG_SYS_POST_CPU
wdenk324f6cf2002-10-07 21:13:39 +0000136 },
137#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500138#if CFG_POST & CFG_SYS_POST_FPU
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400139 {
140 "FPU test",
141 "fpu",
142 "This test verifies the arithmetic logic unit of"
143 " FPU.",
144 POST_RAM | POST_ALWAYS,
145 &fpu_post_test,
146 NULL,
147 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500148 CFG_SYS_POST_FPU
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400149 },
150#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500151#if CFG_POST & CFG_SYS_POST_UART
Tom Rini8eaa3c72022-11-19 18:45:44 -0500152#if defined(CFG_POST_UART)
153 CFG_POST_UART,
Stefan Roese770b00b2010-10-07 14:16:25 +0200154#else
wdenk324f6cf2002-10-07 21:13:39 +0000155 {
wdenk57b2d802003-06-27 21:31:46 +0000156 "UART test",
157 "uart",
158 "This test verifies the UART operation.",
wdenkdccbda02003-07-14 22:13:32 +0000159 POST_RAM | POST_SLOWTEST | POST_MANUAL,
wdenk57b2d802003-06-27 21:31:46 +0000160 &uart_post_test,
161 NULL,
162 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500163 CFG_SYS_POST_UART
wdenk324f6cf2002-10-07 21:13:39 +0000164 },
Tom Rini8eaa3c72022-11-19 18:45:44 -0500165#endif /* CFG_POST_UART */
wdenk324f6cf2002-10-07 21:13:39 +0000166#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500167#if CFG_POST & CFG_SYS_POST_ETHER
wdenk324f6cf2002-10-07 21:13:39 +0000168 {
wdenk57b2d802003-06-27 21:31:46 +0000169 "ETHERNET test",
170 "ethernet",
171 "This test verifies the ETHERNET operation.",
Robert P. J. Day15bdcaf2016-03-27 10:18:55 -0400172 POST_RAM | POST_ALWAYS,
wdenk57b2d802003-06-27 21:31:46 +0000173 &ether_post_test,
174 NULL,
175 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500176 CFG_SYS_POST_ETHER
wdenk324f6cf2002-10-07 21:13:39 +0000177 },
178#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500179#if CFG_POST & CFG_SYS_POST_USB
wdenk324f6cf2002-10-07 21:13:39 +0000180 {
wdenk57b2d802003-06-27 21:31:46 +0000181 "USB test",
182 "usb",
183 "This test verifies the USB operation.",
Robert P. J. Day15bdcaf2016-03-27 10:18:55 -0400184 POST_RAM | POST_ALWAYS,
wdenk57b2d802003-06-27 21:31:46 +0000185 &usb_post_test,
186 NULL,
187 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500188 CFG_SYS_POST_USB
wdenk324f6cf2002-10-07 21:13:39 +0000189 },
190#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500191#if CFG_POST & CFG_SYS_POST_SPR
wdenk324f6cf2002-10-07 21:13:39 +0000192 {
wdenk57b2d802003-06-27 21:31:46 +0000193 "SPR test",
194 "spr",
195 "This test checks SPR contents.",
Stefan Roese191a8dc2008-01-09 10:38:58 +0100196 POST_RAM | POST_ALWAYS,
wdenk57b2d802003-06-27 21:31:46 +0000197 &spr_post_test,
198 NULL,
199 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500200 CFG_SYS_POST_SPR
wdenk324f6cf2002-10-07 21:13:39 +0000201 },
202#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500203#if CFG_POST & CFG_SYS_POST_SYSMON
wdenkc08f1582003-04-27 22:52:51 +0000204 {
wdenk57b2d802003-06-27 21:31:46 +0000205 "SYSMON test",
206 "sysmon",
207 "This test monitors system hardware.",
208 POST_RAM | POST_ALWAYS,
209 &sysmon_post_test,
210 &sysmon_init_f,
211 &sysmon_reloc,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500212 CFG_SYS_POST_SYSMON
wdenkc08f1582003-04-27 22:52:51 +0000213 },
214#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500215#if CFG_POST & CFG_SYS_POST_DSP
wdenk61642172004-04-15 21:16:42 +0000216 {
217 "DSP test",
218 "dsp",
219 "This test checks any connected DSP(s).",
Robert P. J. Day15bdcaf2016-03-27 10:18:55 -0400220 POST_RAM | POST_ALWAYS,
wdenk61642172004-04-15 21:16:42 +0000221 &dsp_post_test,
222 NULL,
223 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500224 CFG_SYS_POST_DSP
wdenk61642172004-04-15 21:16:42 +0000225 },
226#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500227#if CFG_POST & CFG_SYS_POST_CODEC
wdenkc4e854f2004-06-07 23:46:25 +0000228 {
229 "CODEC test",
230 "codec",
231 "This test checks any connected codec(s).",
232 POST_RAM | POST_MANUAL,
233 &codec_post_test,
234 NULL,
235 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500236 CFG_SYS_POST_CODEC
wdenkc4e854f2004-06-07 23:46:25 +0000237 },
238#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500239#if CFG_POST & CFG_SYS_POST_ECC
Pavel Kolesnikov5d896112007-07-20 15:03:03 +0200240 {
241 "ECC test",
242 "ecc",
Larry Johnsonc2abd6e2008-01-12 23:35:33 -0500243 "This test checks the ECC facility of memory.",
244 POST_ROM | POST_ALWAYS | POST_PREREL,
Pavel Kolesnikov5d896112007-07-20 15:03:03 +0200245 &ecc_post_test,
246 NULL,
247 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500248 CFG_SYS_POST_ECC
Pavel Kolesnikov5d896112007-07-20 15:03:03 +0200249 },
250#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500251#if CFG_POST & CFG_SYS_POST_BSPEC1
Tom Rini8eaa3c72022-11-19 18:45:44 -0500252 CFG_POST_BSPEC1,
Yuri Tikhonovc147d482008-02-04 14:10:42 +0100253#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500254#if CFG_POST & CFG_SYS_POST_BSPEC2
Tom Rini8eaa3c72022-11-19 18:45:44 -0500255 CFG_POST_BSPEC2,
Yuri Tikhonovc147d482008-02-04 14:10:42 +0100256#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500257#if CFG_POST & CFG_SYS_POST_BSPEC3
Tom Rini8eaa3c72022-11-19 18:45:44 -0500258 CFG_POST_BSPEC3,
Yuri Tikhonovc147d482008-02-04 14:10:42 +0100259#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500260#if CFG_POST & CFG_SYS_POST_BSPEC4
Tom Rini8eaa3c72022-11-19 18:45:44 -0500261 CFG_POST_BSPEC4,
Yuri Tikhonovc147d482008-02-04 14:10:42 +0100262#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500263#if CFG_POST & CFG_SYS_POST_BSPEC5
Tom Rini8eaa3c72022-11-19 18:45:44 -0500264 CFG_POST_BSPEC5,
Yuri Tikhonovc147d482008-02-04 14:10:42 +0100265#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500266#if CFG_POST & CFG_SYS_POST_COPROC
Anatolij Gustschin810b2072010-04-24 19:27:11 +0200267 {
268 "Coprocessors communication test",
269 "coproc_com",
270 "This test checks communication with coprocessors.",
271 POST_RAM | POST_ALWAYS | POST_CRITICAL,
272 &coprocessor_post_test,
273 NULL,
274 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500275 CFG_SYS_POST_COPROC
Mike Frysinger813531f2011-05-10 13:35:40 +0000276 },
277#endif
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500278#if CFG_POST & CFG_SYS_POST_FLASH
Mike Frysinger813531f2011-05-10 13:35:40 +0000279 {
280 "Parallel NOR flash test",
281 "flash",
282 "This test verifies parallel flash operations.",
283 POST_RAM | POST_SLOWTEST | POST_MANUAL,
284 &flash_post_test,
285 NULL,
286 NULL,
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500287 CFG_SYS_POST_FLASH
Mike Frysinger813531f2011-05-10 13:35:40 +0000288 },
Anatolij Gustschin810b2072010-04-24 19:27:11 +0200289#endif
Tom Rini8eaa3c72022-11-19 18:45:44 -0500290#if CFG_POST & CFG_SYS_POST_MEM_REGIONS
Valentin Longchamp24db42a2011-09-12 04:18:40 +0000291 {
292 "Memory regions test",
293 "mem_regions",
294 "This test checks regularly placed regions of the RAM.",
295 POST_ROM | POST_SLOWTEST | POST_PREREL,
296 &memory_regions_post_test,
297 NULL,
298 NULL,
Tom Rini6a5dccc2022-11-16 13:10:41 -0500299 CFG_SYS_POST_MEM_REGIONS
Valentin Longchamp24db42a2011-09-12 04:18:40 +0000300 },
301#endif
wdenk324f6cf2002-10-07 21:13:39 +0000302};
303
Mike Frysinger83a687b2011-05-10 07:28:35 +0000304unsigned int post_list_size = ARRAY_SIZE(post_list);