Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc |
Yangbo Lu | 023d419 | 2021-06-03 10:51:18 +0800 | [diff] [blame] | 4 | * Copyright 2019, 2021 NXP |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 5 | * Andy Fleming |
| 6 | * Yangbo Lu <yangbo.lu@nxp.com> |
| 7 | * |
| 8 | * Based vaguely on the pxa mmc code: |
| 9 | * (C) Copyright 2003 |
| 10 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
| 11 | */ |
| 12 | |
| 13 | #include <config.h> |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 14 | #include <command.h> |
| 15 | #include <clk.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 16 | #include <cpu_func.h> |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 17 | #include <errno.h> |
| 18 | #include <hwconfig.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 19 | #include <log.h> |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 20 | #include <mmc.h> |
| 21 | #include <part.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 22 | #include <asm/cache.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 23 | #include <asm/global_data.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 24 | #include <dm/device_compat.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 25 | #include <linux/bitops.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 26 | #include <linux/delay.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 27 | #include <linux/err.h> |
Simon Glass | bdd5f81 | 2023-09-14 18:21:46 -0600 | [diff] [blame] | 28 | #include <linux/printk.h> |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 29 | #include <power/regulator.h> |
| 30 | #include <malloc.h> |
| 31 | #include <fsl_esdhc_imx.h> |
| 32 | #include <fdt_support.h> |
| 33 | #include <asm/io.h> |
| 34 | #include <dm.h> |
| 35 | #include <asm-generic/gpio.h> |
| 36 | #include <dm/pinctrl.h> |
Walter Lozano | 8aff673 | 2020-07-29 12:31:17 -0300 | [diff] [blame] | 37 | #include <dt-structs.h> |
| 38 | #include <mapmem.h> |
| 39 | #include <dm/ofnode.h> |
Haibo Chen | e6a999b | 2020-09-01 15:34:06 +0800 | [diff] [blame] | 40 | #include <linux/iopoll.h> |
Sean Anderson | 120fc01 | 2021-11-23 15:03:43 -0500 | [diff] [blame] | 41 | #include <linux/dma-mapping.h> |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 42 | |
Haibo Chen | e8801ac | 2021-02-19 11:25:32 -0800 | [diff] [blame] | 43 | #ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
| 44 | #ifdef CONFIG_FSL_USDHC |
| 45 | #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 |
| 46 | #endif |
| 47 | #endif |
| 48 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 49 | DECLARE_GLOBAL_DATA_PTR; |
| 50 | |
| 51 | #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ |
| 52 | IRQSTATEN_CINT | \ |
| 53 | IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ |
| 54 | IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ |
| 55 | IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ |
| 56 | IRQSTATEN_DINT) |
| 57 | #define MAX_TUNING_LOOP 40 |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 58 | |
| 59 | struct fsl_esdhc { |
| 60 | uint dsaddr; /* SDMA system address register */ |
| 61 | uint blkattr; /* Block attributes register */ |
| 62 | uint cmdarg; /* Command argument register */ |
| 63 | uint xfertyp; /* Transfer type register */ |
| 64 | uint cmdrsp0; /* Command response 0 register */ |
| 65 | uint cmdrsp1; /* Command response 1 register */ |
| 66 | uint cmdrsp2; /* Command response 2 register */ |
| 67 | uint cmdrsp3; /* Command response 3 register */ |
| 68 | uint datport; /* Buffer data port register */ |
| 69 | uint prsstat; /* Present state register */ |
| 70 | uint proctl; /* Protocol control register */ |
| 71 | uint sysctl; /* System Control Register */ |
| 72 | uint irqstat; /* Interrupt status register */ |
| 73 | uint irqstaten; /* Interrupt status enable register */ |
| 74 | uint irqsigen; /* Interrupt signal enable register */ |
| 75 | uint autoc12err; /* Auto CMD error status register */ |
| 76 | uint hostcapblt; /* Host controller capabilities register */ |
| 77 | uint wml; /* Watermark level register */ |
| 78 | uint mixctrl; /* For USDHC */ |
| 79 | char reserved1[4]; /* reserved */ |
| 80 | uint fevt; /* Force event register */ |
| 81 | uint admaes; /* ADMA error status register */ |
| 82 | uint adsaddr; /* ADMA system address register */ |
| 83 | char reserved2[4]; |
| 84 | uint dllctrl; |
| 85 | uint dllstat; |
| 86 | uint clktunectrlstatus; |
| 87 | char reserved3[4]; |
| 88 | uint strobe_dllctrl; |
| 89 | uint strobe_dllstat; |
| 90 | char reserved4[72]; |
| 91 | uint vendorspec; |
| 92 | uint mmcboot; |
| 93 | uint vendorspec2; |
Giulio Benetti | 65b5ec1 | 2020-01-10 15:51:46 +0100 | [diff] [blame] | 94 | uint tuning_ctrl; /* on i.MX6/7/8/RT */ |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 95 | char reserved5[44]; |
| 96 | uint hostver; /* Host controller version register */ |
| 97 | char reserved6[4]; /* reserved */ |
| 98 | uint dmaerraddr; /* DMA error address register */ |
| 99 | char reserved7[4]; /* reserved */ |
| 100 | uint dmaerrattr; /* DMA error attribute register */ |
| 101 | char reserved8[4]; /* reserved */ |
| 102 | uint hostcapblt2; /* Host controller capabilities register 2 */ |
| 103 | char reserved9[8]; /* reserved */ |
| 104 | uint tcr; /* Tuning control register */ |
| 105 | char reserved10[28]; /* reserved */ |
| 106 | uint sddirctl; /* SD direction control register */ |
| 107 | char reserved11[712];/* reserved */ |
| 108 | uint scr; /* eSDHC control register */ |
| 109 | }; |
| 110 | |
| 111 | struct fsl_esdhc_plat { |
Walter Lozano | 8aff673 | 2020-07-29 12:31:17 -0300 | [diff] [blame] | 112 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 113 | /* Put this first since driver model will copy the data here */ |
| 114 | struct dtd_fsl_esdhc dtplat; |
| 115 | #endif |
| 116 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 117 | struct mmc_config cfg; |
| 118 | struct mmc mmc; |
| 119 | }; |
| 120 | |
| 121 | struct esdhc_soc_data { |
| 122 | u32 flags; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 123 | }; |
| 124 | |
| 125 | /** |
| 126 | * struct fsl_esdhc_priv |
| 127 | * |
| 128 | * @esdhc_regs: registers of the sdhc controller |
| 129 | * @sdhc_clk: Current clk of the sdhc controller |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 130 | * @cfg: mmc config |
| 131 | * @mmc: mmc |
| 132 | * Following is used when Driver Model is enabled for MMC |
| 133 | * @dev: pointer for the device |
Fabio Estevam | 7e3d8a9 | 2020-01-06 20:11:27 -0300 | [diff] [blame] | 134 | * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 135 | * @wp_enable: 1: enable checking wp; 0: no check |
| 136 | * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V |
| 137 | * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h |
| 138 | * @caps: controller capabilities |
| 139 | * @tuning_step: tuning step setting in tuning_ctrl register |
| 140 | * @start_tuning_tap: the start point for tuning in tuning_ctrl register |
| 141 | * @strobe_dll_delay_target: settings in strobe_dllctrl |
| 142 | * @signal_voltage: indicating the current voltage |
Haibo Chen | 2615495 | 2021-03-22 18:55:38 +0800 | [diff] [blame] | 143 | * @signal_voltage_switch_extra_delay_ms: extra delay for IO voltage switch |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 144 | * @cd_gpio: gpio for card detection |
| 145 | * @wp_gpio: gpio for write protection |
| 146 | */ |
| 147 | struct fsl_esdhc_priv { |
| 148 | struct fsl_esdhc *esdhc_regs; |
| 149 | unsigned int sdhc_clk; |
| 150 | struct clk per_clk; |
| 151 | unsigned int clock; |
| 152 | unsigned int mode; |
Sean Anderson | 80b8161 | 2022-01-12 08:18:52 +0900 | [diff] [blame] | 153 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 154 | struct mmc *mmc; |
| 155 | #endif |
| 156 | struct udevice *dev; |
Fabio Estevam | 7e3d8a9 | 2020-01-06 20:11:27 -0300 | [diff] [blame] | 157 | int broken_cd; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 158 | int wp_enable; |
| 159 | int vs18_enable; |
| 160 | u32 flags; |
| 161 | u32 caps; |
| 162 | u32 tuning_step; |
| 163 | u32 tuning_start_tap; |
| 164 | u32 strobe_dll_delay_target; |
| 165 | u32 signal_voltage; |
Haibo Chen | 2615495 | 2021-03-22 18:55:38 +0800 | [diff] [blame] | 166 | u32 signal_voltage_switch_extra_delay_ms; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 167 | struct udevice *vqmmc_dev; |
| 168 | struct udevice *vmmc_dev; |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 169 | #if CONFIG_IS_ENABLED(DM_GPIO) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 170 | struct gpio_desc cd_gpio; |
| 171 | struct gpio_desc wp_gpio; |
| 172 | #endif |
Sean Anderson | 120fc01 | 2021-11-23 15:03:43 -0500 | [diff] [blame] | 173 | dma_addr_t dma_addr; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 174 | }; |
| 175 | |
| 176 | /* Return the XFERTYP flags for a given command and data packet */ |
| 177 | static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) |
| 178 | { |
| 179 | uint xfertyp = 0; |
| 180 | |
| 181 | if (data) { |
| 182 | xfertyp |= XFERTYP_DPSEL; |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 183 | if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO) && |
| 184 | cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK && |
| 185 | cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200) |
| 186 | xfertyp |= XFERTYP_DMAEN; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 187 | if (data->blocks > 1) { |
| 188 | xfertyp |= XFERTYP_MSBSEL; |
| 189 | xfertyp |= XFERTYP_BCEN; |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 190 | if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111)) |
| 191 | xfertyp |= XFERTYP_AC12EN; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | if (data->flags & MMC_DATA_READ) |
| 195 | xfertyp |= XFERTYP_DTDSEL; |
| 196 | } |
| 197 | |
| 198 | if (cmd->resp_type & MMC_RSP_CRC) |
| 199 | xfertyp |= XFERTYP_CCCEN; |
| 200 | if (cmd->resp_type & MMC_RSP_OPCODE) |
| 201 | xfertyp |= XFERTYP_CICEN; |
| 202 | if (cmd->resp_type & MMC_RSP_136) |
| 203 | xfertyp |= XFERTYP_RSPTYP_136; |
| 204 | else if (cmd->resp_type & MMC_RSP_BUSY) |
| 205 | xfertyp |= XFERTYP_RSPTYP_48_BUSY; |
| 206 | else if (cmd->resp_type & MMC_RSP_PRESENT) |
| 207 | xfertyp |= XFERTYP_RSPTYP_48; |
| 208 | |
| 209 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 210 | xfertyp |= XFERTYP_CMDTYP_ABORT; |
| 211 | |
| 212 | return XFERTYP_CMD(cmd->cmdidx) | xfertyp; |
| 213 | } |
| 214 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 215 | /* |
| 216 | * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. |
| 217 | */ |
| 218 | static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv, |
| 219 | struct mmc_data *data) |
| 220 | { |
| 221 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 222 | uint blocks; |
| 223 | char *buffer; |
| 224 | uint databuf; |
| 225 | uint size; |
| 226 | uint irqstat; |
| 227 | ulong start; |
| 228 | |
| 229 | if (data->flags & MMC_DATA_READ) { |
| 230 | blocks = data->blocks; |
| 231 | buffer = data->dest; |
| 232 | while (blocks) { |
| 233 | start = get_timer(0); |
| 234 | size = data->blocksize; |
| 235 | irqstat = esdhc_read32(®s->irqstat); |
| 236 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) { |
| 237 | if (get_timer(start) > PIO_TIMEOUT) { |
| 238 | printf("\nData Read Failed in PIO Mode."); |
| 239 | return; |
| 240 | } |
| 241 | } |
| 242 | while (size && (!(irqstat & IRQSTAT_TC))) { |
| 243 | udelay(100); /* Wait before last byte transfer complete */ |
| 244 | irqstat = esdhc_read32(®s->irqstat); |
| 245 | databuf = in_le32(®s->datport); |
| 246 | *((uint *)buffer) = databuf; |
| 247 | buffer += 4; |
| 248 | size -= 4; |
| 249 | } |
| 250 | blocks--; |
| 251 | } |
| 252 | } else { |
| 253 | blocks = data->blocks; |
| 254 | buffer = (char *)data->src; |
| 255 | while (blocks) { |
| 256 | start = get_timer(0); |
| 257 | size = data->blocksize; |
| 258 | irqstat = esdhc_read32(®s->irqstat); |
| 259 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) { |
| 260 | if (get_timer(start) > PIO_TIMEOUT) { |
| 261 | printf("\nData Write Failed in PIO Mode."); |
| 262 | return; |
| 263 | } |
| 264 | } |
| 265 | while (size && (!(irqstat & IRQSTAT_TC))) { |
| 266 | udelay(100); /* Wait before last byte transfer complete */ |
| 267 | databuf = *((uint *)buffer); |
| 268 | buffer += 4; |
| 269 | size -= 4; |
| 270 | irqstat = esdhc_read32(®s->irqstat); |
| 271 | out_le32(®s->datport, databuf); |
| 272 | } |
| 273 | blocks--; |
| 274 | } |
| 275 | } |
| 276 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 277 | |
Sean Anderson | aa6d91d | 2021-11-23 15:03:44 -0500 | [diff] [blame] | 278 | static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv, |
| 279 | struct mmc_data *data) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 280 | { |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 281 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Sean Anderson | aa6d91d | 2021-11-23 15:03:44 -0500 | [diff] [blame] | 282 | uint wml_value = data->blocksize / 4; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 283 | |
| 284 | if (data->flags & MMC_DATA_READ) { |
| 285 | if (wml_value > WML_RD_WML_MAX) |
| 286 | wml_value = WML_RD_WML_MAX_VAL; |
| 287 | |
| 288 | esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 289 | } else { |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 290 | if (wml_value > WML_WR_WML_MAX) |
| 291 | wml_value = WML_WR_WML_MAX_VAL; |
Sean Anderson | aa6d91d | 2021-11-23 15:03:44 -0500 | [diff] [blame] | 292 | |
| 293 | esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, |
| 294 | wml_value << 16); |
| 295 | } |
| 296 | } |
Sean Anderson | aa6d91d | 2021-11-23 15:03:44 -0500 | [diff] [blame] | 297 | |
| 298 | static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data) |
| 299 | { |
| 300 | uint trans_bytes = data->blocksize * data->blocks; |
| 301 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 302 | void *buf; |
| 303 | |
| 304 | if (data->flags & MMC_DATA_WRITE) |
| 305 | buf = (void *)data->src; |
| 306 | else |
| 307 | buf = data->dest; |
| 308 | |
| 309 | priv->dma_addr = dma_map_single(buf, trans_bytes, |
| 310 | mmc_get_dma_dir(data)); |
| 311 | if (upper_32_bits(priv->dma_addr)) |
| 312 | printf("Cannot use 64 bit addresses with SDMA\n"); |
| 313 | esdhc_write32(®s->dsaddr, lower_32_bits(priv->dma_addr)); |
| 314 | esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); |
| 315 | } |
| 316 | |
| 317 | static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, |
| 318 | struct mmc_data *data) |
| 319 | { |
| 320 | int timeout; |
| 321 | bool is_write = data->flags & MMC_DATA_WRITE; |
| 322 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 323 | |
| 324 | if (is_write) { |
| 325 | if (priv->wp_enable && !(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) { |
| 326 | printf("Cannot write to locked SD card.\n"); |
| 327 | return -EINVAL; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 328 | } else { |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 329 | #if CONFIG_IS_ENABLED(DM_GPIO) |
| 330 | if (dm_gpio_is_valid(&priv->wp_gpio) && |
| 331 | dm_gpio_get_value(&priv->wp_gpio)) { |
Sean Anderson | aa6d91d | 2021-11-23 15:03:44 -0500 | [diff] [blame] | 332 | printf("Cannot write to locked SD card.\n"); |
| 333 | return -EINVAL; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 334 | } |
| 335 | #endif |
| 336 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 337 | } |
| 338 | |
Marcel Ziswiler | 86376fd | 2022-01-31 23:08:31 +0100 | [diff] [blame] | 339 | esdhc_setup_watermark_level(priv, data); |
| 340 | if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO)) |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 341 | esdhc_setup_dma(priv, data); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 342 | |
| 343 | /* Calculate the timeout period for data transactions */ |
| 344 | /* |
| 345 | * 1)Timeout period = (2^(timeout+13)) SD Clock cycles |
| 346 | * 2)Timeout period should be minimum 0.250sec as per SD Card spec |
| 347 | * So, Number of SD Clock cycles for 0.25sec should be minimum |
| 348 | * (SD Clock/sec * 0.25 sec) SD Clock cycles |
| 349 | * = (mmc->clock * 1/4) SD Clock cycles |
| 350 | * As 1) >= 2) |
| 351 | * => (2^(timeout+13)) >= mmc->clock * 1/4 |
| 352 | * Taking log2 both the sides |
| 353 | * => timeout + 13 >= log2(mmc->clock/4) |
| 354 | * Rounding up to next power of 2 |
| 355 | * => timeout + 13 = log2(mmc->clock/4) + 1 |
| 356 | * => timeout + 13 = fls(mmc->clock/4) |
| 357 | * |
| 358 | * However, the MMC spec "It is strongly recommended for hosts to |
| 359 | * implement more than 500ms timeout value even if the card |
| 360 | * indicates the 250ms maximum busy length." Even the previous |
| 361 | * value of 300ms is known to be insufficient for some cards. |
| 362 | * So, we use |
| 363 | * => timeout + 13 = fls(mmc->clock/2) |
| 364 | */ |
| 365 | timeout = fls(mmc->clock/2); |
| 366 | timeout -= 13; |
| 367 | |
| 368 | if (timeout > 14) |
| 369 | timeout = 14; |
| 370 | |
| 371 | if (timeout < 0) |
| 372 | timeout = 0; |
| 373 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 374 | if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) && |
| 375 | (timeout == 4 || timeout == 8 || timeout == 12)) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 376 | timeout++; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 377 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 378 | if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE)) |
| 379 | timeout = 0xE; |
| 380 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 381 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); |
| 382 | |
| 383 | return 0; |
| 384 | } |
| 385 | |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 386 | #if IS_ENABLED(CONFIG_MCF5441x) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 387 | /* |
| 388 | * Swaps 32-bit words to little-endian byte order. |
| 389 | */ |
| 390 | static inline void sd_swap_dma_buff(struct mmc_data *data) |
| 391 | { |
| 392 | int i, size = data->blocksize >> 2; |
| 393 | u32 *buffer = (u32 *)data->dest; |
| 394 | u32 sw; |
| 395 | |
| 396 | while (data->blocks--) { |
| 397 | for (i = 0; i < size; i++) { |
| 398 | sw = __sw32(*buffer); |
| 399 | *buffer++ = sw; |
| 400 | } |
| 401 | } |
| 402 | } |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 403 | #else |
| 404 | static inline void sd_swap_dma_buff(struct mmc_data *data) |
| 405 | { |
| 406 | return; |
| 407 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 408 | #endif |
| 409 | |
| 410 | /* |
| 411 | * Sends a command out on the bus. Takes the mmc pointer, |
| 412 | * a command pointer, and an optional data pointer. |
| 413 | */ |
| 414 | static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, |
| 415 | struct mmc_cmd *cmd, struct mmc_data *data) |
| 416 | { |
| 417 | int err = 0; |
| 418 | uint xfertyp; |
| 419 | uint irqstat; |
| 420 | u32 flags = IRQSTAT_CC | IRQSTAT_CTOE; |
| 421 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 422 | unsigned long start; |
| 423 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 424 | if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111) && |
| 425 | cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 426 | return 0; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 427 | |
| 428 | esdhc_write32(®s->irqstat, -1); |
| 429 | |
| 430 | sync(); |
| 431 | |
| 432 | /* Wait for the bus to be idle */ |
| 433 | while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || |
| 434 | (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) |
| 435 | ; |
| 436 | |
| 437 | while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) |
| 438 | ; |
| 439 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 440 | /* Set up for a data transfer if we have one */ |
| 441 | if (data) { |
| 442 | err = esdhc_setup_data(priv, mmc, data); |
| 443 | if(err) |
| 444 | return err; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 445 | } |
| 446 | |
| 447 | /* Figure out the transfer arguments */ |
| 448 | xfertyp = esdhc_xfertyp(cmd, data); |
| 449 | |
| 450 | /* Mask all irqs */ |
| 451 | esdhc_write32(®s->irqsigen, 0); |
| 452 | |
| 453 | /* Send the command */ |
| 454 | esdhc_write32(®s->cmdarg, cmd->cmdarg); |
Simon Glass | 87f79c5 | 2022-01-22 05:07:24 -0700 | [diff] [blame] | 455 | if (IS_ENABLED(CONFIG_FSL_USDHC)) { |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 456 | u32 mixctrl = esdhc_read32(®s->mixctrl); |
| 457 | |
| 458 | esdhc_write32(®s->mixctrl, |
| 459 | (mixctrl & 0xFFFFFF80) | (xfertyp & 0x7F) |
| 460 | | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); |
| 461 | esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); |
| 462 | } else { |
| 463 | esdhc_write32(®s->xfertyp, xfertyp); |
| 464 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 465 | |
| 466 | if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || |
| 467 | (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) |
| 468 | flags = IRQSTAT_BRR; |
| 469 | |
| 470 | /* Wait for the command to complete */ |
| 471 | start = get_timer(0); |
| 472 | while (!(esdhc_read32(®s->irqstat) & flags)) { |
| 473 | if (get_timer(start) > 1000) { |
| 474 | err = -ETIMEDOUT; |
| 475 | goto out; |
| 476 | } |
| 477 | } |
| 478 | |
| 479 | irqstat = esdhc_read32(®s->irqstat); |
| 480 | |
| 481 | if (irqstat & CMD_ERR) { |
| 482 | err = -ECOMM; |
| 483 | goto out; |
| 484 | } |
| 485 | |
| 486 | if (irqstat & IRQSTAT_CTOE) { |
| 487 | err = -ETIMEDOUT; |
| 488 | goto out; |
| 489 | } |
| 490 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 491 | /* Workaround for ESDHC errata ENGcm03648 */ |
| 492 | if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { |
Peng Fan | 3dbea59 | 2019-07-10 09:35:30 +0000 | [diff] [blame] | 493 | int timeout = 50000; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 494 | |
Peng Fan | 3dbea59 | 2019-07-10 09:35:30 +0000 | [diff] [blame] | 495 | /* Poll on DATA0 line for cmd with busy signal for 5000 ms */ |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 496 | while (timeout > 0 && !(esdhc_read32(®s->prsstat) & |
| 497 | PRSSTAT_DAT0)) { |
| 498 | udelay(100); |
| 499 | timeout--; |
| 500 | } |
| 501 | |
| 502 | if (timeout <= 0) { |
| 503 | printf("Timeout waiting for DAT0 to go high!\n"); |
| 504 | err = -ETIMEDOUT; |
| 505 | goto out; |
| 506 | } |
| 507 | } |
| 508 | |
| 509 | /* Copy the response to the response buffer */ |
| 510 | if (cmd->resp_type & MMC_RSP_136) { |
| 511 | u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; |
| 512 | |
| 513 | cmdrsp3 = esdhc_read32(®s->cmdrsp3); |
| 514 | cmdrsp2 = esdhc_read32(®s->cmdrsp2); |
| 515 | cmdrsp1 = esdhc_read32(®s->cmdrsp1); |
| 516 | cmdrsp0 = esdhc_read32(®s->cmdrsp0); |
| 517 | cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); |
| 518 | cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); |
| 519 | cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); |
| 520 | cmd->response[3] = (cmdrsp0 << 8); |
| 521 | } else |
| 522 | cmd->response[0] = esdhc_read32(®s->cmdrsp0); |
| 523 | |
| 524 | /* Wait until all of the blocks are transferred */ |
| 525 | if (data) { |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 526 | if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO)) { |
| 527 | esdhc_pio_read_write(priv, data); |
| 528 | } else { |
| 529 | flags = DATA_COMPLETE; |
| 530 | if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || |
| 531 | cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) |
| 532 | flags = IRQSTAT_BRR; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 533 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 534 | do { |
| 535 | irqstat = esdhc_read32(®s->irqstat); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 536 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 537 | if (irqstat & IRQSTAT_DTOE) { |
| 538 | err = -ETIMEDOUT; |
| 539 | goto out; |
| 540 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 541 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 542 | if (irqstat & DATA_ERR) { |
| 543 | err = -ECOMM; |
| 544 | goto out; |
| 545 | } |
| 546 | } while ((irqstat & flags) != flags); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 547 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 548 | /* |
| 549 | * Need invalidate the dcache here again to avoid any |
| 550 | * cache-fill during the DMA operations such as the |
| 551 | * speculative pre-fetching etc. |
| 552 | */ |
| 553 | dma_unmap_single(priv->dma_addr, |
| 554 | data->blocks * data->blocksize, |
| 555 | mmc_get_dma_dir(data)); |
| 556 | if (IS_ENABLED(CONFIG_MCF5441x) && |
| 557 | (data->flags & MMC_DATA_READ)) |
| 558 | sd_swap_dma_buff(data); |
| 559 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 560 | } |
| 561 | |
| 562 | out: |
| 563 | /* Reset CMD and DATA portions on error */ |
| 564 | if (err) { |
| 565 | esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | |
| 566 | SYSCTL_RSTC); |
| 567 | while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) |
| 568 | ; |
| 569 | |
| 570 | if (data) { |
| 571 | esdhc_write32(®s->sysctl, |
| 572 | esdhc_read32(®s->sysctl) | |
| 573 | SYSCTL_RSTD); |
| 574 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) |
| 575 | ; |
| 576 | } |
| 577 | |
| 578 | /* If this was CMD11, then notify that power cycle is needed */ |
| 579 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) |
| 580 | printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); |
| 581 | } |
| 582 | |
| 583 | esdhc_write32(®s->irqstat, -1); |
| 584 | |
| 585 | return err; |
| 586 | } |
| 587 | |
| 588 | static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) |
| 589 | { |
| 590 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 591 | int div = 1; |
Haibo Chen | e6a999b | 2020-09-01 15:34:06 +0800 | [diff] [blame] | 592 | u32 tmp; |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 593 | int ret, pre_div; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 594 | int ddr_pre_div = mmc->ddr_mode ? 2 : 1; |
| 595 | int sdhc_clk = priv->sdhc_clk; |
| 596 | uint clk; |
| 597 | |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 598 | #if IS_ENABLED(CONFIG_MX53) |
Haibo Chen | 84516a7 | 2022-02-11 19:16:56 +0800 | [diff] [blame] | 599 | /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ |
| 600 | pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1; |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 601 | #else |
Haibo Chen | 84516a7 | 2022-02-11 19:16:56 +0800 | [diff] [blame] | 602 | pre_div = 1; |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 603 | #endif |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 604 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 605 | while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) |
| 606 | pre_div *= 2; |
| 607 | |
| 608 | while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) |
| 609 | div++; |
| 610 | |
Haibo Chen | 8be0ba3 | 2022-02-11 19:16:57 +0800 | [diff] [blame] | 611 | mmc->clock = sdhc_clk / pre_div / div / ddr_pre_div; |
| 612 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 613 | pre_div >>= 1; |
| 614 | div -= 1; |
| 615 | |
| 616 | clk = (pre_div << 8) | (div << 4); |
| 617 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 618 | if (IS_ENABLED(CONFIG_FSL_USDHC)) |
| 619 | esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); |
| 620 | else |
| 621 | esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 622 | |
| 623 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); |
| 624 | |
Haibo Chen | e6a999b | 2020-09-01 15:34:06 +0800 | [diff] [blame] | 625 | ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100); |
| 626 | if (ret) |
| 627 | pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n"); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 628 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 629 | if (IS_ENABLED(CONFIG_FSL_USDHC)) |
| 630 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); |
| 631 | else |
| 632 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 633 | |
| 634 | priv->clock = clock; |
| 635 | } |
| 636 | |
Tom Rini | c1edd47 | 2024-05-01 19:30:18 -0600 | [diff] [blame] | 637 | #if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 638 | static int esdhc_change_pinstate(struct udevice *dev) |
| 639 | { |
| 640 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 641 | int ret; |
| 642 | |
| 643 | switch (priv->mode) { |
| 644 | case UHS_SDR50: |
| 645 | case UHS_DDR50: |
| 646 | ret = pinctrl_select_state(dev, "state_100mhz"); |
| 647 | break; |
| 648 | case UHS_SDR104: |
| 649 | case MMC_HS_200: |
| 650 | case MMC_HS_400: |
Peng Fan | 69b9d3a | 2019-07-10 09:35:26 +0000 | [diff] [blame] | 651 | case MMC_HS_400_ES: |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 652 | ret = pinctrl_select_state(dev, "state_200mhz"); |
| 653 | break; |
| 654 | default: |
| 655 | ret = pinctrl_select_state(dev, "default"); |
| 656 | break; |
| 657 | } |
| 658 | |
| 659 | if (ret) |
| 660 | printf("%s %d error\n", __func__, priv->mode); |
| 661 | |
| 662 | return ret; |
| 663 | } |
| 664 | |
| 665 | static void esdhc_reset_tuning(struct mmc *mmc) |
| 666 | { |
| 667 | struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); |
| 668 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 669 | |
| 670 | if (priv->flags & ESDHC_FLAG_USDHC) { |
| 671 | if (priv->flags & ESDHC_FLAG_STD_TUNING) { |
| 672 | esdhc_clrbits32(®s->autoc12err, |
| 673 | MIX_CTRL_SMPCLK_SEL | |
| 674 | MIX_CTRL_EXE_TUNE); |
| 675 | } |
| 676 | } |
| 677 | } |
| 678 | |
| 679 | static void esdhc_set_strobe_dll(struct mmc *mmc) |
| 680 | { |
| 681 | struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); |
| 682 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 683 | u32 val; |
| 684 | |
| 685 | if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 686 | esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET); |
Oleksandr Suvorov | d4245c2 | 2021-09-08 21:56:43 +0300 | [diff] [blame] | 687 | /* clear the reset bit on strobe dll before any setting */ |
| 688 | esdhc_write32(®s->strobe_dllctrl, 0); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 689 | |
| 690 | /* |
| 691 | * enable strobe dll ctrl and adjust the delay target |
| 692 | * for the uSDHC loopback read clock |
| 693 | */ |
| 694 | val = ESDHC_STROBE_DLL_CTRL_ENABLE | |
Oleksandr Suvorov | d4245c2 | 2021-09-08 21:56:43 +0300 | [diff] [blame] | 695 | ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 696 | (priv->strobe_dll_delay_target << |
| 697 | ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 698 | esdhc_write32(®s->strobe_dllctrl, val); |
Oleksandr Suvorov | d4245c2 | 2021-09-08 21:56:43 +0300 | [diff] [blame] | 699 | /* wait 5us to make sure strobe dll status register stable */ |
| 700 | mdelay(5); |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 701 | val = esdhc_read32(®s->strobe_dllstat); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 702 | if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK)) |
| 703 | pr_warn("HS400 strobe DLL status REF not lock!\n"); |
| 704 | if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) |
| 705 | pr_warn("HS400 strobe DLL status SLV not lock!\n"); |
| 706 | } |
| 707 | } |
| 708 | |
| 709 | static int esdhc_set_timing(struct mmc *mmc) |
| 710 | { |
| 711 | struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); |
| 712 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 713 | u32 mixctrl; |
| 714 | |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 715 | mixctrl = esdhc_read32(®s->mixctrl); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 716 | mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN); |
| 717 | |
| 718 | switch (mmc->selected_mode) { |
| 719 | case MMC_LEGACY: |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 720 | esdhc_reset_tuning(mmc); |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 721 | esdhc_write32(®s->mixctrl, mixctrl); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 722 | break; |
| 723 | case MMC_HS_400: |
Peng Fan | 69b9d3a | 2019-07-10 09:35:26 +0000 | [diff] [blame] | 724 | case MMC_HS_400_ES: |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 725 | mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN; |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 726 | esdhc_write32(®s->mixctrl, mixctrl); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 727 | break; |
| 728 | case MMC_HS: |
| 729 | case MMC_HS_52: |
| 730 | case MMC_HS_200: |
| 731 | case SD_HS: |
| 732 | case UHS_SDR12: |
| 733 | case UHS_SDR25: |
| 734 | case UHS_SDR50: |
| 735 | case UHS_SDR104: |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 736 | esdhc_write32(®s->mixctrl, mixctrl); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 737 | break; |
| 738 | case UHS_DDR50: |
| 739 | case MMC_DDR_52: |
| 740 | mixctrl |= MIX_CTRL_DDREN; |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 741 | esdhc_write32(®s->mixctrl, mixctrl); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 742 | break; |
| 743 | default: |
| 744 | printf("Not supported %d\n", mmc->selected_mode); |
| 745 | return -EINVAL; |
| 746 | } |
| 747 | |
| 748 | priv->mode = mmc->selected_mode; |
| 749 | |
| 750 | return esdhc_change_pinstate(mmc->dev); |
| 751 | } |
| 752 | |
| 753 | static int esdhc_set_voltage(struct mmc *mmc) |
| 754 | { |
| 755 | struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); |
| 756 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 757 | int ret; |
| 758 | |
| 759 | priv->signal_voltage = mmc->signal_voltage; |
| 760 | switch (mmc->signal_voltage) { |
| 761 | case MMC_SIGNAL_VOLTAGE_330: |
| 762 | if (priv->vs18_enable) |
Marek Vasut | ba79fed | 2020-05-22 18:28:33 +0200 | [diff] [blame] | 763 | return -ENOTSUPP; |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 764 | if (CONFIG_IS_ENABLED(DM_REGULATOR) && |
| 765 | !IS_ERR_OR_NULL(priv->vqmmc_dev)) { |
| 766 | ret = regulator_set_value(priv->vqmmc_dev, |
| 767 | 3300000); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 768 | if (ret) { |
| 769 | printf("Setting to 3.3V error"); |
| 770 | return -EIO; |
| 771 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 772 | mdelay(5); |
| 773 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 774 | |
| 775 | esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); |
| 776 | if (!(esdhc_read32(®s->vendorspec) & |
| 777 | ESDHC_VENDORSPEC_VSELECT)) |
| 778 | return 0; |
| 779 | |
| 780 | return -EAGAIN; |
| 781 | case MMC_SIGNAL_VOLTAGE_180: |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 782 | if (CONFIG_IS_ENABLED(DM_REGULATOR) && |
| 783 | !IS_ERR_OR_NULL(priv->vqmmc_dev)) { |
| 784 | ret = regulator_set_value(priv->vqmmc_dev, |
| 785 | 1800000); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 786 | if (ret) { |
| 787 | printf("Setting to 1.8V error"); |
| 788 | return -EIO; |
| 789 | } |
| 790 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 791 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); |
Haibo Chen | 2615495 | 2021-03-22 18:55:38 +0800 | [diff] [blame] | 792 | /* |
| 793 | * some board like imx8mm-evk need about 18ms to switch |
| 794 | * the IO voltage from 3.3v to 1.8v, common code only |
| 795 | * delay 10ms, so need to delay extra time to make sure |
| 796 | * the IO voltage change to 1.8v. |
| 797 | */ |
| 798 | if (priv->signal_voltage_switch_extra_delay_ms) |
| 799 | mdelay(priv->signal_voltage_switch_extra_delay_ms); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 800 | if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT) |
| 801 | return 0; |
| 802 | |
| 803 | return -EAGAIN; |
| 804 | case MMC_SIGNAL_VOLTAGE_120: |
| 805 | return -ENOTSUPP; |
| 806 | default: |
| 807 | return 0; |
| 808 | } |
| 809 | } |
| 810 | |
| 811 | static void esdhc_stop_tuning(struct mmc *mmc) |
| 812 | { |
| 813 | struct mmc_cmd cmd; |
| 814 | |
| 815 | cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; |
| 816 | cmd.cmdarg = 0; |
| 817 | cmd.resp_type = MMC_RSP_R1b; |
| 818 | |
Jaehoon Chung | 099814b | 2021-05-31 08:31:49 +0900 | [diff] [blame] | 819 | mmc_send_cmd(mmc, &cmd, NULL); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 820 | } |
| 821 | |
| 822 | static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) |
| 823 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 824 | struct fsl_esdhc_plat *plat = dev_get_plat(dev); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 825 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 826 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 827 | struct mmc *mmc = &plat->mmc; |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 828 | u32 irqstaten = esdhc_read32(®s->irqstaten); |
| 829 | u32 irqsigen = esdhc_read32(®s->irqsigen); |
Haibo Chen | 3a385c8 | 2022-02-22 11:28:18 +0800 | [diff] [blame] | 830 | int i, err, ret = -ETIMEDOUT; |
| 831 | u32 val, mixctrl, tmp; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 832 | |
| 833 | /* clock tuning is not needed for upto 52MHz */ |
| 834 | if (mmc->clock <= 52000000) |
| 835 | return 0; |
| 836 | |
Haibo Chen | 3a385c8 | 2022-02-22 11:28:18 +0800 | [diff] [blame] | 837 | /* make sure the card clock keep on */ |
| 838 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); |
| 839 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 840 | /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */ |
| 841 | if (priv->flags & ESDHC_FLAG_STD_TUNING) { |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 842 | val = esdhc_read32(®s->autoc12err); |
| 843 | mixctrl = esdhc_read32(®s->mixctrl); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 844 | val &= ~MIX_CTRL_SMPCLK_SEL; |
| 845 | mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN); |
| 846 | |
| 847 | val |= MIX_CTRL_EXE_TUNE; |
| 848 | mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN; |
| 849 | |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 850 | esdhc_write32(®s->autoc12err, val); |
| 851 | esdhc_write32(®s->mixctrl, mixctrl); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 852 | } |
| 853 | |
| 854 | /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */ |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 855 | mixctrl = esdhc_read32(®s->mixctrl); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 856 | mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK); |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 857 | esdhc_write32(®s->mixctrl, mixctrl); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 858 | |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 859 | esdhc_write32(®s->irqstaten, IRQSTATEN_BRR); |
| 860 | esdhc_write32(®s->irqsigen, IRQSTATEN_BRR); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 861 | |
| 862 | /* |
| 863 | * Issue opcode repeatedly till Execute Tuning is set to 0 or the number |
| 864 | * of loops reaches 40 times. |
| 865 | */ |
| 866 | for (i = 0; i < MAX_TUNING_LOOP; i++) { |
| 867 | u32 ctrl; |
| 868 | |
| 869 | if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) { |
| 870 | if (mmc->bus_width == 8) |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 871 | esdhc_write32(®s->blkattr, 0x7080); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 872 | else if (mmc->bus_width == 4) |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 873 | esdhc_write32(®s->blkattr, 0x7040); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 874 | } else { |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 875 | esdhc_write32(®s->blkattr, 0x7040); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 876 | } |
| 877 | |
| 878 | /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */ |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 879 | val = esdhc_read32(®s->mixctrl); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 880 | val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK); |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 881 | esdhc_write32(®s->mixctrl, val); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 882 | |
| 883 | /* We are using STD tuning, no need to check return value */ |
Marek Vasut | dad81fb | 2024-02-20 09:36:23 +0100 | [diff] [blame] | 884 | mmc_send_tuning(mmc, opcode); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 885 | |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 886 | ctrl = esdhc_read32(®s->autoc12err); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 887 | if ((!(ctrl & MIX_CTRL_EXE_TUNE)) && |
| 888 | (ctrl & MIX_CTRL_SMPCLK_SEL)) { |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 889 | ret = 0; |
| 890 | break; |
| 891 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 892 | } |
| 893 | |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 894 | esdhc_write32(®s->irqstaten, irqstaten); |
| 895 | esdhc_write32(®s->irqsigen, irqsigen); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 896 | |
| 897 | esdhc_stop_tuning(mmc); |
| 898 | |
Haibo Chen | 3a385c8 | 2022-02-22 11:28:18 +0800 | [diff] [blame] | 899 | /* change to default setting, let host control the card clock */ |
| 900 | esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); |
| 901 | err = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); |
| 902 | if (err) |
| 903 | dev_warn(dev, "card clock not gate off as expect.\n"); |
| 904 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 905 | return ret; |
| 906 | } |
| 907 | #endif |
| 908 | |
| 909 | static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) |
| 910 | { |
| 911 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 912 | int ret __maybe_unused; |
Peng Fan | 2cdf52b | 2019-11-04 17:14:15 +0800 | [diff] [blame] | 913 | u32 clock; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 914 | |
Tom Rini | c1edd47 | 2024-05-01 19:30:18 -0600 | [diff] [blame] | 915 | #if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) |
Haibo Chen | eaa2f10 | 2020-11-03 17:18:35 +0800 | [diff] [blame] | 916 | /* |
| 917 | * call esdhc_set_timing() before update the clock rate, |
| 918 | * This is because current we support DDR and SDR mode, |
| 919 | * Once the DDR_EN bit is set, the card clock will be |
| 920 | * divide by 2 automatically. So need to do this before |
| 921 | * setting clock rate. |
| 922 | */ |
| 923 | if (priv->mode != mmc->selected_mode) { |
| 924 | ret = esdhc_set_timing(mmc); |
| 925 | if (ret) { |
| 926 | printf("esdhc_set_timing error %d\n", ret); |
| 927 | return ret; |
| 928 | } |
| 929 | } |
| 930 | #endif |
| 931 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 932 | /* Set the clock speed */ |
Peng Fan | 2cdf52b | 2019-11-04 17:14:15 +0800 | [diff] [blame] | 933 | clock = mmc->clock; |
| 934 | if (clock < mmc->cfg->f_min) |
| 935 | clock = mmc->cfg->f_min; |
| 936 | |
| 937 | if (priv->clock != clock) |
| 938 | set_sysctl(priv, mmc, clock); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 939 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 940 | if (mmc->clk_disable) { |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 941 | if (IS_ENABLED(CONFIG_FSL_USDHC)) |
| 942 | esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); |
| 943 | else |
| 944 | esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 945 | } else { |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 946 | if (IS_ENABLED(CONFIG_FSL_USDHC)) |
| 947 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | |
| 948 | VENDORSPEC_CKEN); |
| 949 | else |
| 950 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 951 | } |
| 952 | |
Tom Rini | c1edd47 | 2024-05-01 19:30:18 -0600 | [diff] [blame] | 953 | #if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) |
Haibo Chen | eaa2f10 | 2020-11-03 17:18:35 +0800 | [diff] [blame] | 954 | /* |
| 955 | * For HS400/HS400ES mode, make sure set the strobe dll in the |
| 956 | * target clock rate. So call esdhc_set_strobe_dll() after the |
| 957 | * clock updated. |
| 958 | */ |
| 959 | if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) |
| 960 | esdhc_set_strobe_dll(mmc); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 961 | |
| 962 | if (priv->signal_voltage != mmc->signal_voltage) { |
| 963 | ret = esdhc_set_voltage(mmc); |
| 964 | if (ret) { |
Marek Vasut | ba79fed | 2020-05-22 18:28:33 +0200 | [diff] [blame] | 965 | if (ret != -ENOTSUPP) |
| 966 | printf("esdhc_set_voltage error %d\n", ret); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 967 | return ret; |
| 968 | } |
| 969 | } |
| 970 | #endif |
| 971 | |
| 972 | /* Set the bus width */ |
| 973 | esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); |
| 974 | |
| 975 | if (mmc->bus_width == 4) |
| 976 | esdhc_setbits32(®s->proctl, PROCTL_DTW_4); |
| 977 | else if (mmc->bus_width == 8) |
| 978 | esdhc_setbits32(®s->proctl, PROCTL_DTW_8); |
| 979 | |
| 980 | return 0; |
| 981 | } |
| 982 | |
| 983 | static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) |
| 984 | { |
| 985 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 986 | ulong start; |
| 987 | |
| 988 | /* Reset the entire host controller */ |
| 989 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
| 990 | |
| 991 | /* Wait until the controller is available */ |
| 992 | start = get_timer(0); |
| 993 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { |
| 994 | if (get_timer(start) > 1000) |
| 995 | return -ETIMEDOUT; |
| 996 | } |
| 997 | |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 998 | if (IS_ENABLED(CONFIG_FSL_USDHC)) { |
| 999 | /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ |
| 1000 | esdhc_write32(®s->mmcboot, 0x0); |
| 1001 | /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ |
| 1002 | esdhc_write32(®s->mixctrl, 0x0); |
| 1003 | esdhc_write32(®s->clktunectrlstatus, 0x0); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1004 | |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1005 | /* Put VEND_SPEC to default value */ |
| 1006 | if (priv->vs18_enable) |
| 1007 | esdhc_write32(®s->vendorspec, VENDORSPEC_INIT | |
| 1008 | ESDHC_VENDORSPEC_VSELECT); |
| 1009 | else |
| 1010 | esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1011 | |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1012 | /* Disable DLL_CTRL delay line */ |
| 1013 | esdhc_write32(®s->dllctrl, 0x0); |
| 1014 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1015 | |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1016 | if (IS_ENABLED(CONFIG_FSL_USDHC)) |
| 1017 | esdhc_setbits32(®s->vendorspec, |
| 1018 | VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); |
| 1019 | else |
| 1020 | esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1021 | |
| 1022 | /* Set the initial clock speed */ |
Sean Anderson | ab3d154 | 2021-11-23 15:03:47 -0500 | [diff] [blame] | 1023 | set_sysctl(priv, mmc, 400000); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1024 | |
| 1025 | /* Disable the BRR and BWR bits in IRQSTAT */ |
| 1026 | esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |
| 1027 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1028 | /* Put the PROCTL reg back to the default */ |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1029 | if (IS_ENABLED(CONFIG_MCF5441x)) |
| 1030 | esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD); |
| 1031 | else |
| 1032 | esdhc_write32(®s->proctl, PROCTL_INIT); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1033 | |
| 1034 | /* Set timout to the maximum value */ |
| 1035 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); |
| 1036 | |
| 1037 | return 0; |
| 1038 | } |
| 1039 | |
| 1040 | static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) |
| 1041 | { |
| 1042 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 1043 | int timeout = 1000; |
| 1044 | |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1045 | if (IS_ENABLED(CONFIG_ESDHC_DETECT_QUIRK)) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1046 | return 1; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1047 | |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1048 | if (CONFIG_IS_ENABLED(DM_MMC)) { |
| 1049 | if (priv->broken_cd) |
| 1050 | return 1; |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 1051 | #if CONFIG_IS_ENABLED(DM_GPIO) |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1052 | if (dm_gpio_is_valid(&priv->cd_gpio)) |
| 1053 | return dm_gpio_get_value(&priv->cd_gpio); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1054 | #endif |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1055 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1056 | |
| 1057 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) |
| 1058 | udelay(1000); |
| 1059 | |
| 1060 | return timeout > 0; |
| 1061 | } |
| 1062 | |
Loic Poulain | 233c373 | 2022-05-26 16:37:22 +0200 | [diff] [blame] | 1063 | static int esdhc_wait_dat0_common(struct fsl_esdhc_priv *priv, int state, |
| 1064 | int timeout_us) |
| 1065 | { |
| 1066 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 1067 | int ret, err; |
| 1068 | u32 tmp; |
| 1069 | |
| 1070 | /* make sure the card clock keep on */ |
| 1071 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); |
| 1072 | |
| 1073 | ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, |
| 1074 | !!(tmp & PRSSTAT_DAT0) == !!state, |
| 1075 | timeout_us); |
| 1076 | |
| 1077 | /* change to default setting, let host control the card clock */ |
| 1078 | esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); |
| 1079 | |
| 1080 | err = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); |
| 1081 | if (err) |
| 1082 | pr_warn("card clock not gate off as expect.\n"); |
| 1083 | |
| 1084 | return ret; |
| 1085 | } |
| 1086 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1087 | static int esdhc_reset(struct fsl_esdhc *regs) |
| 1088 | { |
| 1089 | ulong start; |
| 1090 | |
| 1091 | /* reset the controller */ |
| 1092 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
| 1093 | |
| 1094 | /* hardware clears the bit when it is done */ |
| 1095 | start = get_timer(0); |
| 1096 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { |
| 1097 | if (get_timer(start) > 100) { |
| 1098 | printf("MMC/SD: Reset never completed.\n"); |
| 1099 | return -ETIMEDOUT; |
| 1100 | } |
| 1101 | } |
| 1102 | |
| 1103 | return 0; |
| 1104 | } |
| 1105 | |
| 1106 | #if !CONFIG_IS_ENABLED(DM_MMC) |
| 1107 | static int esdhc_getcd(struct mmc *mmc) |
| 1108 | { |
| 1109 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 1110 | |
| 1111 | return esdhc_getcd_common(priv); |
| 1112 | } |
| 1113 | |
| 1114 | static int esdhc_init(struct mmc *mmc) |
| 1115 | { |
| 1116 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 1117 | |
| 1118 | return esdhc_init_common(priv, mmc); |
| 1119 | } |
| 1120 | |
| 1121 | static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
| 1122 | struct mmc_data *data) |
| 1123 | { |
| 1124 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 1125 | |
| 1126 | return esdhc_send_cmd_common(priv, mmc, cmd, data); |
| 1127 | } |
| 1128 | |
| 1129 | static int esdhc_set_ios(struct mmc *mmc) |
| 1130 | { |
| 1131 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 1132 | |
| 1133 | return esdhc_set_ios_common(priv, mmc); |
| 1134 | } |
| 1135 | |
Loic Poulain | 233c373 | 2022-05-26 16:37:22 +0200 | [diff] [blame] | 1136 | static int esdhc_wait_dat0(struct mmc *mmc, int state, int timeout_us) |
| 1137 | { |
| 1138 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 1139 | |
| 1140 | return esdhc_wait_dat0_common(priv, state, timeout_us); |
| 1141 | } |
| 1142 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1143 | static const struct mmc_ops esdhc_ops = { |
| 1144 | .getcd = esdhc_getcd, |
| 1145 | .init = esdhc_init, |
| 1146 | .send_cmd = esdhc_send_cmd, |
| 1147 | .set_ios = esdhc_set_ios, |
Loic Poulain | 233c373 | 2022-05-26 16:37:22 +0200 | [diff] [blame] | 1148 | .wait_dat0 = esdhc_wait_dat0, |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1149 | }; |
| 1150 | #endif |
| 1151 | |
| 1152 | static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, |
| 1153 | struct fsl_esdhc_plat *plat) |
| 1154 | { |
| 1155 | struct mmc_config *cfg; |
| 1156 | struct fsl_esdhc *regs; |
Sean Anderson | 6dff7b7 | 2021-11-23 15:03:38 -0500 | [diff] [blame] | 1157 | u32 caps; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1158 | int ret; |
| 1159 | |
| 1160 | if (!priv) |
| 1161 | return -EINVAL; |
| 1162 | |
| 1163 | regs = priv->esdhc_regs; |
| 1164 | |
| 1165 | /* First reset the eSDHC controller */ |
| 1166 | ret = esdhc_reset(regs); |
| 1167 | if (ret) |
| 1168 | return ret; |
| 1169 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1170 | /* ColdFire, using SDHC_DATA[3] for card detection */ |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 1171 | if (IS_ENABLED(CONFIG_MCF5441x)) |
| 1172 | esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1173 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 1174 | if (IS_ENABLED(CONFIG_FSL_USDHC)) { |
| 1175 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | |
| 1176 | VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); |
| 1177 | } else { |
| 1178 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
| 1179 | | SYSCTL_IPGEN | SYSCTL_CKEN); |
| 1180 | /* Clearing tuning bits in case ROM has set it already */ |
| 1181 | esdhc_write32(®s->mixctrl, 0); |
| 1182 | esdhc_write32(®s->autoc12err, 0); |
| 1183 | esdhc_write32(®s->clktunectrlstatus, 0); |
| 1184 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1185 | |
| 1186 | if (priv->vs18_enable) |
| 1187 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); |
| 1188 | |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 1189 | esdhc_write32(®s->irqstaten, SDHCI_IRQ_EN_BITS); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1190 | cfg = &plat->cfg; |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1191 | if (!CONFIG_IS_ENABLED(DM_MMC)) |
| 1192 | memset(cfg, '\0', sizeof(*cfg)); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1193 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1194 | caps = esdhc_read32(®s->hostcapblt); |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 1195 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1196 | /* |
| 1197 | * MCF5441x RM declares in more points that sdhc clock speed must |
| 1198 | * never exceed 25 Mhz. From this, the HS bit needs to be disabled |
| 1199 | * from host capabilities. |
| 1200 | */ |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 1201 | if (IS_ENABLED(CONFIG_MCF5441x)) |
| 1202 | caps &= ~HOSTCAPBLT_HSS; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1203 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 1204 | if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135)) |
| 1205 | caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30); |
Sean Anderson | 6dff7b7 | 2021-11-23 15:03:38 -0500 | [diff] [blame] | 1206 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 1207 | if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33)) |
| 1208 | caps |= HOSTCAPBLT_VS33; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1209 | |
Sean Anderson | 6dff7b7 | 2021-11-23 15:03:38 -0500 | [diff] [blame] | 1210 | if (caps & HOSTCAPBLT_VS18) |
| 1211 | cfg->voltages |= MMC_VDD_165_195; |
| 1212 | if (caps & HOSTCAPBLT_VS30) |
| 1213 | cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; |
| 1214 | if (caps & HOSTCAPBLT_VS33) |
| 1215 | cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1216 | |
| 1217 | cfg->name = "FSL_SDHC"; |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 1218 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1219 | #if !CONFIG_IS_ENABLED(DM_MMC) |
| 1220 | cfg->ops = &esdhc_ops; |
| 1221 | #endif |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1222 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 1223 | if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE)) |
| 1224 | cfg->host_caps |= MMC_MODE_DDR_52MHz; |
| 1225 | |
Sean Anderson | 6dff7b7 | 2021-11-23 15:03:38 -0500 | [diff] [blame] | 1226 | if (caps & HOSTCAPBLT_HSS) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1227 | cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
| 1228 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1229 | cfg->host_caps |= priv->caps; |
| 1230 | |
| 1231 | cfg->f_min = 400000; |
| 1232 | cfg->f_max = min(priv->sdhc_clk, (u32)200000000); |
| 1233 | |
| 1234 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
| 1235 | |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 1236 | esdhc_write32(®s->dllctrl, 0); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1237 | if (priv->flags & ESDHC_FLAG_USDHC) { |
| 1238 | if (priv->flags & ESDHC_FLAG_STD_TUNING) { |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 1239 | u32 val = esdhc_read32(®s->tuning_ctrl); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1240 | |
| 1241 | val |= ESDHC_STD_TUNING_EN; |
| 1242 | val &= ~ESDHC_TUNING_START_TAP_MASK; |
| 1243 | val |= priv->tuning_start_tap; |
| 1244 | val &= ~ESDHC_TUNING_STEP_MASK; |
| 1245 | val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT; |
Haibo Chen | 43162c3 | 2020-06-22 19:38:04 +0800 | [diff] [blame] | 1246 | |
| 1247 | /* Disable the CMD CRC check for tuning, if not, need to |
| 1248 | * add some delay after every tuning command, because |
| 1249 | * hardware standard tuning logic will directly go to next |
| 1250 | * step once it detect the CMD CRC error, will not wait for |
| 1251 | * the card side to finally send out the tuning data, trigger |
| 1252 | * the buffer read ready interrupt immediately. If usdhc send |
| 1253 | * the next tuning command some eMMC card will stuck, can't |
| 1254 | * response, block the tuning procedure or the first command |
| 1255 | * after the whole tuning procedure always can't get any response. |
| 1256 | */ |
| 1257 | val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE; |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 1258 | esdhc_write32(®s->tuning_ctrl, val); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1259 | } |
Adam Ford | 97497fd | 2022-01-12 07:53:56 -0600 | [diff] [blame] | 1260 | |
| 1261 | /* |
| 1262 | * UHS doesn't have explicit ESDHC flags, so if it's |
| 1263 | * not supported, disable it in config. |
| 1264 | */ |
| 1265 | if (CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)) |
| 1266 | cfg->host_caps |= UHS_CAPS; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1267 | |
Adam Ford | 97497fd | 2022-01-12 07:53:56 -0600 | [diff] [blame] | 1268 | if (CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)) { |
| 1269 | if (priv->flags & ESDHC_FLAG_HS200) |
| 1270 | cfg->host_caps |= MMC_CAP(MMC_HS_200); |
| 1271 | } |
| 1272 | |
| 1273 | if (CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)) { |
| 1274 | if (priv->flags & ESDHC_FLAG_HS400) |
| 1275 | cfg->host_caps |= MMC_CAP(MMC_HS_400); |
| 1276 | } |
| 1277 | |
| 1278 | if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)) { |
| 1279 | if (priv->flags & ESDHC_FLAG_HS400_ES) |
| 1280 | cfg->host_caps |= MMC_CAP(MMC_HS_400_ES); |
| 1281 | } |
| 1282 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1283 | return 0; |
| 1284 | } |
| 1285 | |
| 1286 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 1287 | int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1288 | { |
| 1289 | struct fsl_esdhc_plat *plat; |
| 1290 | struct fsl_esdhc_priv *priv; |
Sean Anderson | 1f0d6c6 | 2021-11-23 15:03:39 -0500 | [diff] [blame] | 1291 | struct mmc_config *mmc_cfg; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1292 | struct mmc *mmc; |
| 1293 | int ret; |
| 1294 | |
| 1295 | if (!cfg) |
| 1296 | return -EINVAL; |
| 1297 | |
| 1298 | priv = calloc(sizeof(struct fsl_esdhc_priv), 1); |
| 1299 | if (!priv) |
| 1300 | return -ENOMEM; |
| 1301 | plat = calloc(sizeof(struct fsl_esdhc_plat), 1); |
| 1302 | if (!plat) { |
| 1303 | free(priv); |
| 1304 | return -ENOMEM; |
| 1305 | } |
| 1306 | |
Sean Anderson | 1f0d6c6 | 2021-11-23 15:03:39 -0500 | [diff] [blame] | 1307 | priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); |
| 1308 | priv->sdhc_clk = cfg->sdhc_clk; |
| 1309 | priv->wp_enable = cfg->wp_enable; |
| 1310 | |
| 1311 | mmc_cfg = &plat->cfg; |
| 1312 | |
| 1313 | switch (cfg->max_bus_width) { |
| 1314 | case 0: /* Not set in config; assume everything is supported */ |
| 1315 | case 8: |
| 1316 | mmc_cfg->host_caps |= MMC_MODE_8BIT; |
| 1317 | fallthrough; |
| 1318 | case 4: |
| 1319 | mmc_cfg->host_caps |= MMC_MODE_4BIT; |
| 1320 | fallthrough; |
| 1321 | case 1: |
| 1322 | mmc_cfg->host_caps |= MMC_MODE_1BIT; |
| 1323 | break; |
| 1324 | default: |
| 1325 | printf("invalid max bus width %u\n", cfg->max_bus_width); |
| 1326 | return -EINVAL; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1327 | } |
| 1328 | |
Sean Anderson | 218dfa1 | 2021-11-23 15:03:45 -0500 | [diff] [blame] | 1329 | if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK)) |
Sean Anderson | 1f0d6c6 | 2021-11-23 15:03:39 -0500 | [diff] [blame] | 1330 | mmc_cfg->host_caps &= ~MMC_MODE_8BIT; |
Sean Anderson | 1f0d6c6 | 2021-11-23 15:03:39 -0500 | [diff] [blame] | 1331 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1332 | ret = fsl_esdhc_init(priv, plat); |
| 1333 | if (ret) { |
| 1334 | debug("%s init failure\n", __func__); |
| 1335 | free(plat); |
| 1336 | free(priv); |
| 1337 | return ret; |
| 1338 | } |
| 1339 | |
| 1340 | mmc = mmc_create(&plat->cfg, priv); |
| 1341 | if (!mmc) |
| 1342 | return -EIO; |
| 1343 | |
| 1344 | priv->mmc = mmc; |
| 1345 | |
| 1346 | return 0; |
| 1347 | } |
| 1348 | |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 1349 | int fsl_esdhc_mmc_init(struct bd_info *bis) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1350 | { |
| 1351 | struct fsl_esdhc_cfg *cfg; |
| 1352 | |
| 1353 | cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 1354 | cfg->esdhc_base = CFG_SYS_FSL_ESDHC_ADDR; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1355 | cfg->sdhc_clk = gd->arch.sdhc_clk; |
| 1356 | return fsl_esdhc_initialize(bis, cfg); |
| 1357 | } |
| 1358 | #endif |
| 1359 | |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1360 | #if CONFIG_IS_ENABLED(OF_LIBFDT) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1361 | __weak int esdhc_status_fixup(void *blob, const char *compat) |
| 1362 | { |
Tom Rini | f8967f8 | 2022-12-02 16:42:22 -0500 | [diff] [blame] | 1363 | if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) { |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1364 | do_fixup_by_compat(blob, compat, "status", "disabled", |
| 1365 | sizeof("disabled"), 1); |
| 1366 | return 1; |
| 1367 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1368 | return 0; |
| 1369 | } |
| 1370 | |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 1371 | void fdt_fixup_esdhc(void *blob, struct bd_info *bd) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1372 | { |
| 1373 | const char *compat = "fsl,esdhc"; |
| 1374 | |
| 1375 | if (esdhc_status_fixup(blob, compat)) |
| 1376 | return; |
| 1377 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1378 | do_fixup_by_compat_u32(blob, compat, "clock-frequency", |
| 1379 | gd->arch.sdhc_clk, 1); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1380 | } |
| 1381 | #endif |
| 1382 | |
| 1383 | #if CONFIG_IS_ENABLED(DM_MMC) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1384 | #include <asm/arch/clock.h> |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1385 | __weak void init_clk_usdhc(u32 index) |
| 1386 | { |
| 1387 | } |
| 1388 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 1389 | static int fsl_esdhc_of_to_plat(struct udevice *dev) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1390 | { |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1391 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1392 | struct udevice *vqmmc_dev; |
Walter Lozano | 8aff673 | 2020-07-29 12:31:17 -0300 | [diff] [blame] | 1393 | int ret; |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1394 | |
Walter Lozano | 8aff673 | 2020-07-29 12:31:17 -0300 | [diff] [blame] | 1395 | const void *fdt = gd->fdt_blob; |
| 1396 | int node = dev_of_offset(dev); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1397 | fdt_addr_t addr; |
| 1398 | unsigned int val; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1399 | |
Simon Glass | 6d70ba0 | 2021-08-07 07:24:06 -0600 | [diff] [blame] | 1400 | if (!CONFIG_IS_ENABLED(OF_REAL)) |
| 1401 | return 0; |
| 1402 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1403 | addr = dev_read_addr(dev); |
| 1404 | if (addr == FDT_ADDR_T_NONE) |
| 1405 | return -EINVAL; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1406 | priv->esdhc_regs = (struct fsl_esdhc *)addr; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1407 | priv->dev = dev; |
| 1408 | priv->mode = -1; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1409 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1410 | val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1); |
| 1411 | priv->tuning_step = val; |
| 1412 | val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap", |
| 1413 | ESDHC_TUNING_START_TAP_DEFAULT); |
| 1414 | priv->tuning_start_tap = val; |
| 1415 | val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target", |
| 1416 | ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT); |
| 1417 | priv->strobe_dll_delay_target = val; |
Haibo Chen | 2615495 | 2021-03-22 18:55:38 +0800 | [diff] [blame] | 1418 | val = fdtdec_get_int(fdt, node, "fsl,signal-voltage-switch-extra-delay-ms", 0); |
| 1419 | priv->signal_voltage_switch_extra_delay_ms = val; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1420 | |
Fabio Estevam | 7e3d8a9 | 2020-01-06 20:11:27 -0300 | [diff] [blame] | 1421 | if (dev_read_bool(dev, "broken-cd")) |
| 1422 | priv->broken_cd = 1; |
| 1423 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1424 | if (dev_read_prop(dev, "fsl,wp-controller", NULL)) { |
| 1425 | priv->wp_enable = 1; |
| 1426 | } else { |
| 1427 | priv->wp_enable = 0; |
Sean Anderson | 5b8040b | 2021-11-23 15:03:40 -0500 | [diff] [blame] | 1428 | } |
| 1429 | |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 1430 | #if CONFIG_IS_ENABLED(DM_GPIO) |
Sean Anderson | 5b8040b | 2021-11-23 15:03:40 -0500 | [diff] [blame] | 1431 | gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, |
| 1432 | GPIOD_IS_IN); |
| 1433 | gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, |
| 1434 | GPIOD_IS_IN); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1435 | #endif |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1436 | |
| 1437 | priv->vs18_enable = 0; |
| 1438 | |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1439 | if (!CONFIG_IS_ENABLED(DM_REGULATOR)) |
| 1440 | return 0; |
| 1441 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1442 | /* |
| 1443 | * If emmc I/O has a fixed voltage at 1.8V, this must be provided, |
| 1444 | * otherwise, emmc will work abnormally. |
| 1445 | */ |
| 1446 | ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev); |
| 1447 | if (ret) { |
| 1448 | dev_dbg(dev, "no vqmmc-supply\n"); |
| 1449 | } else { |
Marek Vasut | 34e67f9 | 2020-05-22 18:19:08 +0200 | [diff] [blame] | 1450 | priv->vqmmc_dev = vqmmc_dev; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1451 | ret = regulator_set_enable(vqmmc_dev, true); |
| 1452 | if (ret) { |
| 1453 | dev_err(dev, "fail to enable vqmmc-supply\n"); |
| 1454 | return ret; |
| 1455 | } |
| 1456 | |
| 1457 | if (regulator_get_value(vqmmc_dev) == 1800000) |
| 1458 | priv->vs18_enable = 1; |
| 1459 | } |
Walter Lozano | 8aff673 | 2020-07-29 12:31:17 -0300 | [diff] [blame] | 1460 | return 0; |
| 1461 | } |
| 1462 | |
| 1463 | static int fsl_esdhc_probe(struct udevice *dev) |
| 1464 | { |
| 1465 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 1466 | struct fsl_esdhc_plat *plat = dev_get_plat(dev); |
Walter Lozano | 8aff673 | 2020-07-29 12:31:17 -0300 | [diff] [blame] | 1467 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 1468 | struct esdhc_soc_data *data = |
| 1469 | (struct esdhc_soc_data *)dev_get_driver_data(dev); |
| 1470 | struct mmc *mmc; |
Walter Lozano | 8aff673 | 2020-07-29 12:31:17 -0300 | [diff] [blame] | 1471 | int ret; |
| 1472 | |
| 1473 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 1474 | struct dtd_fsl_esdhc *dtplat = &plat->dtplat; |
Walter Lozano | 8aff673 | 2020-07-29 12:31:17 -0300 | [diff] [blame] | 1475 | |
| 1476 | priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]); |
Walter Lozano | cfc05fd | 2020-07-29 12:31:19 -0300 | [diff] [blame] | 1477 | |
| 1478 | if (dtplat->non_removable) |
Sean Anderson | 5b8040b | 2021-11-23 15:03:40 -0500 | [diff] [blame] | 1479 | plat->cfg.host_caps |= MMC_CAP_NONREMOVABLE; |
Walter Lozano | cfc05fd | 2020-07-29 12:31:19 -0300 | [diff] [blame] | 1480 | else |
Sean Anderson | 5b8040b | 2021-11-23 15:03:40 -0500 | [diff] [blame] | 1481 | plat->cfg.host_caps &= ~MMC_CAP_NONREMOVABLE; |
Walter Lozano | cfc05fd | 2020-07-29 12:31:19 -0300 | [diff] [blame] | 1482 | |
Sean Anderson | 5b8040b | 2021-11-23 15:03:40 -0500 | [diff] [blame] | 1483 | if (CONFIG_IS_ENABLED(DM_GPIO) && !dtplat->non_removable) { |
Walter Lozano | cfc05fd | 2020-07-29 12:31:19 -0300 | [diff] [blame] | 1484 | struct udevice *gpiodev; |
Walter Lozano | cfc05fd | 2020-07-29 12:31:19 -0300 | [diff] [blame] | 1485 | |
Simon Glass | 0000e0d | 2021-03-15 17:25:28 +1300 | [diff] [blame] | 1486 | ret = device_get_by_ofplat_idx(dtplat->cd_gpios->idx, &gpiodev); |
Walter Lozano | cfc05fd | 2020-07-29 12:31:19 -0300 | [diff] [blame] | 1487 | if (ret) |
| 1488 | return ret; |
| 1489 | |
| 1490 | ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios", |
| 1491 | dtplat->cd_gpios->arg[0], GPIOD_IS_IN, |
| 1492 | dtplat->cd_gpios->arg[1], &priv->cd_gpio); |
| 1493 | |
| 1494 | if (ret) |
| 1495 | return ret; |
| 1496 | } |
Walter Lozano | 8aff673 | 2020-07-29 12:31:17 -0300 | [diff] [blame] | 1497 | #endif |
| 1498 | |
| 1499 | if (data) |
| 1500 | priv->flags = data->flags; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1501 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1502 | /* |
| 1503 | * TODO: |
| 1504 | * Because lack of clk driver, if SDHC clk is not enabled, |
| 1505 | * need to enable it first before this driver is invoked. |
| 1506 | * |
| 1507 | * we use MXC_ESDHC_CLK to get clk freq. |
| 1508 | * If one would like to make this function work, |
| 1509 | * the aliases should be provided in dts as this: |
| 1510 | * |
| 1511 | * aliases { |
| 1512 | * mmc0 = &usdhc1; |
| 1513 | * mmc1 = &usdhc2; |
| 1514 | * mmc2 = &usdhc3; |
| 1515 | * mmc3 = &usdhc4; |
| 1516 | * }; |
| 1517 | * Then if your board only supports mmc2 and mmc3, but we can |
| 1518 | * correctly get the seq as 2 and 3, then let mxc_get_clock |
| 1519 | * work as expected. |
| 1520 | */ |
| 1521 | |
Giulio Benetti | dbdbc63 | 2020-01-10 15:51:45 +0100 | [diff] [blame] | 1522 | #if CONFIG_IS_ENABLED(CLK) |
| 1523 | /* Assigned clock already set clock */ |
| 1524 | ret = clk_get_by_name(dev, "per", &priv->per_clk); |
| 1525 | if (ret) { |
| 1526 | printf("Failed to get per_clk\n"); |
| 1527 | return ret; |
| 1528 | } |
| 1529 | ret = clk_enable(&priv->per_clk); |
| 1530 | if (ret) { |
| 1531 | printf("Failed to enable per_clk\n"); |
| 1532 | return ret; |
| 1533 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1534 | |
Giulio Benetti | dbdbc63 | 2020-01-10 15:51:45 +0100 | [diff] [blame] | 1535 | priv->sdhc_clk = clk_get_rate(&priv->per_clk); |
| 1536 | #else |
Ye Li | 2a4b3b9 | 2022-09-24 00:29:33 +0200 | [diff] [blame] | 1537 | init_clk_usdhc(dev_seq(dev)); |
| 1538 | |
Simon Glass | 75e534b | 2020-12-16 21:20:07 -0700 | [diff] [blame] | 1539 | priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev_seq(dev)); |
Giulio Benetti | dbdbc63 | 2020-01-10 15:51:45 +0100 | [diff] [blame] | 1540 | if (priv->sdhc_clk <= 0) { |
| 1541 | dev_err(dev, "Unable to get clk for %s\n", dev->name); |
| 1542 | return -EINVAL; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1543 | } |
Giulio Benetti | dbdbc63 | 2020-01-10 15:51:45 +0100 | [diff] [blame] | 1544 | #endif |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1545 | |
| 1546 | ret = fsl_esdhc_init(priv, plat); |
| 1547 | if (ret) { |
| 1548 | dev_err(dev, "fsl_esdhc_init failure\n"); |
| 1549 | return ret; |
| 1550 | } |
| 1551 | |
Simon Glass | 6d70ba0 | 2021-08-07 07:24:06 -0600 | [diff] [blame] | 1552 | if (CONFIG_IS_ENABLED(OF_REAL)) { |
| 1553 | ret = mmc_of_parse(dev, &plat->cfg); |
| 1554 | if (ret) |
| 1555 | return ret; |
| 1556 | } |
Peng Fan | 3766a48 | 2019-07-10 09:35:24 +0000 | [diff] [blame] | 1557 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1558 | mmc = &plat->mmc; |
| 1559 | mmc->cfg = &plat->cfg; |
| 1560 | mmc->dev = dev; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1561 | |
| 1562 | upriv->mmc = mmc; |
| 1563 | |
| 1564 | return esdhc_init_common(priv, mmc); |
| 1565 | } |
| 1566 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1567 | static int fsl_esdhc_get_cd(struct udevice *dev) |
| 1568 | { |
Sean Anderson | 5b8040b | 2021-11-23 15:03:40 -0500 | [diff] [blame] | 1569 | struct fsl_esdhc_plat *plat = dev_get_plat(dev); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1570 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 1571 | |
Sean Anderson | 5b8040b | 2021-11-23 15:03:40 -0500 | [diff] [blame] | 1572 | if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE) |
| 1573 | return 1; |
| 1574 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1575 | return esdhc_getcd_common(priv); |
| 1576 | } |
| 1577 | |
| 1578 | static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
| 1579 | struct mmc_data *data) |
| 1580 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 1581 | struct fsl_esdhc_plat *plat = dev_get_plat(dev); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1582 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 1583 | |
| 1584 | return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data); |
| 1585 | } |
| 1586 | |
| 1587 | static int fsl_esdhc_set_ios(struct udevice *dev) |
| 1588 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 1589 | struct fsl_esdhc_plat *plat = dev_get_plat(dev); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1590 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 1591 | |
| 1592 | return esdhc_set_ios_common(priv, &plat->mmc); |
| 1593 | } |
| 1594 | |
Sean Anderson | 3e33079 | 2021-11-23 15:03:46 -0500 | [diff] [blame] | 1595 | static int __maybe_unused fsl_esdhc_set_enhanced_strobe(struct udevice *dev) |
Peng Fan | 69b9d3a | 2019-07-10 09:35:26 +0000 | [diff] [blame] | 1596 | { |
| 1597 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 1598 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 1599 | u32 m; |
| 1600 | |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 1601 | m = esdhc_read32(®s->mixctrl); |
Peng Fan | 69b9d3a | 2019-07-10 09:35:26 +0000 | [diff] [blame] | 1602 | m |= MIX_CTRL_HS400_ES; |
Haibo Chen | 920f5d0 | 2020-09-30 15:52:23 +0800 | [diff] [blame] | 1603 | esdhc_write32(®s->mixctrl, m); |
Peng Fan | 69b9d3a | 2019-07-10 09:35:26 +0000 | [diff] [blame] | 1604 | |
| 1605 | return 0; |
| 1606 | } |
Peng Fan | 69b9d3a | 2019-07-10 09:35:26 +0000 | [diff] [blame] | 1607 | |
Haibo Chen | cb78f21 | 2020-11-05 14:57:13 +0800 | [diff] [blame] | 1608 | static int fsl_esdhc_wait_dat0(struct udevice *dev, int state, |
| 1609 | int timeout_us) |
| 1610 | { |
Haibo Chen | cb78f21 | 2020-11-05 14:57:13 +0800 | [diff] [blame] | 1611 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
Haibo Chen | 3a385c8 | 2022-02-22 11:28:18 +0800 | [diff] [blame] | 1612 | |
Loic Poulain | 233c373 | 2022-05-26 16:37:22 +0200 | [diff] [blame] | 1613 | return esdhc_wait_dat0_common(priv, state, timeout_us); |
Haibo Chen | cb78f21 | 2020-11-05 14:57:13 +0800 | [diff] [blame] | 1614 | } |
| 1615 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1616 | static const struct dm_mmc_ops fsl_esdhc_ops = { |
| 1617 | .get_cd = fsl_esdhc_get_cd, |
| 1618 | .send_cmd = fsl_esdhc_send_cmd, |
| 1619 | .set_ios = fsl_esdhc_set_ios, |
Tom Rini | c1edd47 | 2024-05-01 19:30:18 -0600 | [diff] [blame] | 1620 | #if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1621 | .execute_tuning = fsl_esdhc_execute_tuning, |
| 1622 | #endif |
Peng Fan | 69b9d3a | 2019-07-10 09:35:26 +0000 | [diff] [blame] | 1623 | #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) |
| 1624 | .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe, |
| 1625 | #endif |
Haibo Chen | cb78f21 | 2020-11-05 14:57:13 +0800 | [diff] [blame] | 1626 | .wait_dat0 = fsl_esdhc_wait_dat0, |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1627 | }; |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1628 | |
| 1629 | static struct esdhc_soc_data usdhc_imx7d_data = { |
| 1630 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
| 1631 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
| 1632 | | ESDHC_FLAG_HS400, |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1633 | }; |
| 1634 | |
Jorge Ramirez-Ortiz | 8239e82 | 2021-09-08 21:56:42 +0300 | [diff] [blame] | 1635 | static struct esdhc_soc_data usdhc_imx7ulp_data = { |
| 1636 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
Oleksandr Suvorov | d4245c2 | 2021-09-08 21:56:43 +0300 | [diff] [blame] | 1637 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
| 1638 | | ESDHC_FLAG_HS400, |
Jorge Ramirez-Ortiz | 8239e82 | 2021-09-08 21:56:42 +0300 | [diff] [blame] | 1639 | }; |
| 1640 | |
Peng Fan | 457fe96 | 2019-07-10 09:35:28 +0000 | [diff] [blame] | 1641 | static struct esdhc_soc_data usdhc_imx8qm_data = { |
| 1642 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | |
| 1643 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 | |
| 1644 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES, |
| 1645 | }; |
| 1646 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1647 | static const struct udevice_id fsl_esdhc_ids[] = { |
Fabio Estevam | eaf8ccc | 2021-02-15 08:58:15 -0300 | [diff] [blame] | 1648 | { .compatible = "fsl,imx51-esdhc", }, |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1649 | { .compatible = "fsl,imx53-esdhc", }, |
| 1650 | { .compatible = "fsl,imx6ul-usdhc", }, |
| 1651 | { .compatible = "fsl,imx6sx-usdhc", }, |
| 1652 | { .compatible = "fsl,imx6sl-usdhc", }, |
| 1653 | { .compatible = "fsl,imx6q-usdhc", }, |
| 1654 | { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,}, |
Jorge Ramirez-Ortiz | 8239e82 | 2021-09-08 21:56:42 +0300 | [diff] [blame] | 1655 | { .compatible = "fsl,imx7ulp-usdhc", .data = (ulong)&usdhc_imx7ulp_data,}, |
Peng Fan | 457fe96 | 2019-07-10 09:35:28 +0000 | [diff] [blame] | 1656 | { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, |
Peng Fan | d7689fa | 2019-11-04 17:31:17 +0800 | [diff] [blame] | 1657 | { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, |
| 1658 | { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, |
Marek Vasut | 104704b | 2022-03-10 21:27:04 +0100 | [diff] [blame] | 1659 | { .compatible = "fsl,imx8mp-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, |
Peng Fan | d7689fa | 2019-11-04 17:31:17 +0800 | [diff] [blame] | 1660 | { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, |
Giulio Benetti | 65b5ec1 | 2020-01-10 15:51:46 +0100 | [diff] [blame] | 1661 | { .compatible = "fsl,imxrt-usdhc", }, |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1662 | { .compatible = "fsl,esdhc", }, |
| 1663 | { /* sentinel */ } |
| 1664 | }; |
| 1665 | |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1666 | static int fsl_esdhc_bind(struct udevice *dev) |
| 1667 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 1668 | struct fsl_esdhc_plat *plat = dev_get_plat(dev); |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1669 | |
| 1670 | return mmc_bind(dev, &plat->mmc, &plat->cfg); |
| 1671 | } |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1672 | |
| 1673 | U_BOOT_DRIVER(fsl_esdhc) = { |
Walter Lozano | 904b0be | 2020-07-29 12:31:16 -0300 | [diff] [blame] | 1674 | .name = "fsl_esdhc", |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1675 | .id = UCLASS_MMC, |
| 1676 | .of_match = fsl_esdhc_ids, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 1677 | .of_to_plat = fsl_esdhc_of_to_plat, |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1678 | .ops = &fsl_esdhc_ops, |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1679 | .bind = fsl_esdhc_bind, |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1680 | .probe = fsl_esdhc_probe, |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 1681 | .plat_auto = sizeof(struct fsl_esdhc_plat), |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 1682 | .priv_auto = sizeof(struct fsl_esdhc_priv), |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1683 | }; |
Walter Lozano | 8aff673 | 2020-07-29 12:31:17 -0300 | [diff] [blame] | 1684 | |
Simon Glass | df65db8 | 2020-12-28 20:34:57 -0700 | [diff] [blame] | 1685 | DM_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc) |
Yangbo Lu | 982f425 | 2019-06-21 11:42:27 +0800 | [diff] [blame] | 1686 | #endif |