Blame - board/freescale/mx6sxsabresd/imximage.cfg - filogic/uboot

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Tom Rini	10e4779	2018-05-06 17:58:06 -0400	[diff] [blame]	1	/* SPDX-License-Identifier: GPL-2.0+ */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	2	/*
				3	* Copyright (C) 2014 Freescale Semiconductor, Inc.
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	4	*/
				5
				6	#define __ASSEMBLY__
				7	#include <config.h>
				8
				9	/* image version */
				10
				11	IMAGE_VERSION 2
				12
				13	/*
				14	* Boot Device : one of
				15	* spi/sd/nand/onenand, qspi/nor
				16	*/
				17
				18	BOOT_FROM sd
				19
				20	/*
				21	* Device Configuration Data (DCD)
				22	*
				23	* Each entry must have the format:
				24	* Addr-type Address Value
				25	*
				26	* where:
				27	* Addr-type register length (1,2 or 4 bytes)
				28	* Address absolute address of the register
				29	* value value to be stored in the register
				30	*/
				31
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	32	/* Enable all clocks */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	33	DATA 4 0x020c4068 0xffffffff
				34	DATA 4 0x020c406c 0xffffffff
				35	DATA 4 0x020c4070 0xffffffff
				36	DATA 4 0x020c4074 0xffffffff
				37	DATA 4 0x020c4078 0xffffffff
				38	DATA 4 0x020c407c 0xffffffff
				39	DATA 4 0x020c4080 0xffffffff
				40	DATA 4 0x020c4084 0xffffffff
				41
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	42	/* IOMUX - DDR IO Type */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	43	DATA 4 0x020e0618 0x000c0000
				44	DATA 4 0x020e05fc 0x00000000
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	45
				46	/* Clock */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	47	DATA 4 0x020e032c 0x00000030
				48
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	49	/* Address */
				50	DATA 4 0x020e0300 0x00000020
				51	DATA 4 0x020e02fc 0x00000020
				52	DATA 4 0x020e05f4 0x00000020
				53
				54	/* Control */
				55	DATA 4 0x020e0340 0x00000020
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	56
				57	DATA 4 0x020e0320 0x00000000
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	58	DATA 4 0x020e0310 0x00000020
				59	DATA 4 0x020e0314 0x00000020
				60	DATA 4 0x020e0614 0x00000020
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	61
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	62	/* Data Strobe */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	63	DATA 4 0x020e05f8 0x00020000
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	64	DATA 4 0x020e0330 0x00000028
				65	DATA 4 0x020e0334 0x00000028
				66	DATA 4 0x020e0338 0x00000028
				67	DATA 4 0x020e033c 0x00000028
				68
				69	/* Data */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	70	DATA 4 0x020e0608 0x00020000
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	71	DATA 4 0x020e060c 0x00000028
				72	DATA 4 0x020e0610 0x00000028
				73	DATA 4 0x020e061c 0x00000028
				74	DATA 4 0x020e0620 0x00000028
				75	DATA 4 0x020e02ec 0x00000028
				76	DATA 4 0x020e02f0 0x00000028
				77	DATA 4 0x020e02f4 0x00000028
				78	DATA 4 0x020e02f8 0x00000028
				79
				80	/* Calibrations - ZQ */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	81	DATA 4 0x021b0800 0xa1390003
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	82
				83	/* Write leveling */
				84	DATA 4 0x021b080c 0x00290025
				85	DATA 4 0x021b0810 0x00220022
				86
				87	/* DQS Read Gate */
				88	DATA 4 0x021b083c 0x41480144
				89	DATA 4 0x021b0840 0x01340130
				90
				91	/* Read/Write Delay */
				92	DATA 4 0x021b0848 0x3C3E4244
				93	DATA 4 0x021b0850 0x34363638
				94
				95	/* Read data bit delay */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	96	DATA 4 0x021b081c 0x33333333
				97	DATA 4 0x021b0820 0x33333333
				98	DATA 4 0x021b0824 0x33333333
				99	DATA 4 0x021b0828 0x33333333
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	100
				101	/* Complete calibration by forced measurement */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	102	DATA 4 0x021b08b8 0x00000800
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	103
				104	/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	105	DATA 4 0x021b0004 0x0002002d
				106	DATA 4 0x021b0008 0x00333030
				107	DATA 4 0x021b000c 0x676b52f3
				108	DATA 4 0x021b0010 0xb66d8b63
				109	DATA 4 0x021b0014 0x01ff00db
				110	DATA 4 0x021b0018 0x00011740
				111	DATA 4 0x021b001c 0x00008000
				112	DATA 4 0x021b002c 0x000026d2
				113	DATA 4 0x021b0030 0x006b1023
				114	DATA 4 0x021b0040 0x0000005f
				115	DATA 4 0x021b0000 0x84190000
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	116
				117	/* Initialize MT41K256M16HA-125 - MR2 */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	118	DATA 4 0x021b001c 0x04008032
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	119	/* MR3 */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	120	DATA 4 0x021b001c 0x00008033
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	121	/* MR1 */
				122	DATA 4 0x021b001c 0x00048031
				123	/* MR0 */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	124	DATA 4 0x021b001c 0x05208030
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	125	/* DDR device ZQ calibration */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	126	DATA 4 0x021b001c 0x04008040
Fabio Estevam	44beebb	2014-08-15 01:00:48 -0300	[diff] [blame]	127
				128	/* Final DDR setup, before operation start */
Fabio Estevam	b6936d7	2014-06-24 17:41:01 -0300	[diff] [blame]	129	DATA 4 0x021b0020 0x00000800
				130	DATA 4 0x021b0818 0x00011117
				131	DATA 4 0x021b001c 0x00000000