blob: 1d61f8dc378da51aa26e891fb674ab1f63de9f48 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stephen Warren3b940fa2016-09-13 10:45:59 -06002/*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
Stephen Warren3b940fa2016-09-13 10:45:59 -06004 */
5
Stephen Warren3b940fa2016-09-13 10:45:59 -06006#include <clk-uclass.h>
7#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -07009#include <malloc.h>
Stephen Warren3b940fa2016-09-13 10:45:59 -060010#include <asm/arch/clock.h>
11#include <asm/arch-tegra/clk_rst.h>
12
13static int tegra_car_clk_request(struct clk *clk)
14{
15 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
16 clk->id);
17
18 /*
19 * Note that the first PERIPH_ID_COUNT clock IDs (where the value
20 * varies per SoC) are the peripheral clocks, which use a numbering
21 * scheme that matches HW registers 1:1. There are other clock IDs
22 * beyond this that are assigned arbitrarily by the Tegra CAR DT
23 * binding. Due to the implementation of this driver, it currently
24 * only supports the peripheral IDs.
25 */
26 if (clk->id >= PERIPH_ID_COUNT)
27 return -EINVAL;
28
29 return 0;
30}
31
Stephen Warren3b940fa2016-09-13 10:45:59 -060032static ulong tegra_car_clk_get_rate(struct clk *clk)
33{
34 enum clock_id parent;
35
36 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
37 clk->id);
38
39 parent = clock_get_periph_parent(clk->id);
40 return clock_get_periph_rate(clk->id, parent);
41}
42
43static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
44{
45 enum clock_id parent;
46
47 debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
48 clk->dev, clk->id);
49
50 parent = clock_get_periph_parent(clk->id);
51 return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
52}
53
54static int tegra_car_clk_enable(struct clk *clk)
55{
56 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
57 clk->id);
58
59 clock_enable(clk->id);
60
61 return 0;
62}
63
64static int tegra_car_clk_disable(struct clk *clk)
65{
66 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
67 clk->id);
68
69 clock_disable(clk->id);
70
71 return 0;
72}
73
74static struct clk_ops tegra_car_clk_ops = {
75 .request = tegra_car_clk_request,
Stephen Warren3b940fa2016-09-13 10:45:59 -060076 .get_rate = tegra_car_clk_get_rate,
77 .set_rate = tegra_car_clk_set_rate,
78 .enable = tegra_car_clk_enable,
79 .disable = tegra_car_clk_disable,
80};
81
82static int tegra_car_clk_probe(struct udevice *dev)
83{
84 debug("%s(dev=%p)\n", __func__, dev);
85
86 return 0;
87}
88
89U_BOOT_DRIVER(tegra_car_clk) = {
90 .name = "tegra_car_clk",
91 .id = UCLASS_CLK,
92 .probe = tegra_car_clk_probe,
93 .ops = &tegra_car_clk_ops,
94};