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git01.mediatek.com / filogic / uboot / ab4de134c7240a784816deb00e7e5c9cbdf5277f / . / arch / arm / dts / tegra30-microsoft-surface-rt.dts
blob: 6810350a90bc17301606c6bbb2ce825b7cc44a02 [file] [log] [blame]
Jonas Schwöbelc2e77e62022-01-24 18:06:33 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/input/input.h>
5#include "tegra30.dtsi"
6
7/ {
8 model = "Microsoft Surface RT Tablet";
9 compatible = "microsoft,surface-rt", "nvidia,tegra30";
10
11 chosen {
12 stdout-path = &uarta;
13 };
14
15 aliases {
16 i2c0 = &pwr_i2c;
17
18 mmc0 = &sdmmc4; /* eMMC */
19 mmc1 = &sdmmc1; /* uSD slot */
20
21 rtc0 = &pmic;
22 rtc1 = "/rtc@7000e000";
23
24 spi0 = &spi4;
25
26 usb0 = &usb1;
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0x80000000 0x80000000>;
32 };
33
34 host1x@50000000 {
35 dc@54200000 {
36 rgb {
37 status = "okay";
38
39 nvidia,panel = <&panel>;
40 };
41 };
42 };
43
44 gpio@6000d000 {
45 /* in case usb vbus is on for some reason */
46 usb-vbus-hog {
47 gpio-hog;
48 gpios = <TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
49 output-low;
50 };
51 };
52
53 pinmux@70000868 {
54 pinctrl-names = "default";
55 pinctrl-0 = <&state_default>;
56
57 state_default: pinmux {
58 /* SDMMC1 pinmux */
59 sdmmc1-clk {
60 nvidia,pins = "sdmmc1_clk_pz0";
61 nvidia,function = "sdmmc1";
62 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
63 nvidia,tristate = <TEGRA_PIN_DISABLE>;
64 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
65 };
66 sdmmc1-cmd {
67 nvidia,pins = "sdmmc1_dat3_py4",
68 "sdmmc1_dat2_py5",
69 "sdmmc1_dat1_py6",
70 "sdmmc1_dat0_py7",
71 "sdmmc1_cmd_pz1";
72 nvidia,function = "sdmmc1";
73 nvidia,pull = <TEGRA_PIN_PULL_UP>;
74 nvidia,tristate = <TEGRA_PIN_DISABLE>;
75 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
76 };
77
78 /* SDMMC3 pinmux */
79 sdmmc3-clk {
80 nvidia,pins = "sdmmc3_clk_pa6";
81 nvidia,function = "sdmmc3";
82 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
83 nvidia,tristate = <TEGRA_PIN_DISABLE>;
84 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
85 };
86 sdmmc3-cmd {
87 nvidia,pins = "sdmmc3_cmd_pa7",
88 "sdmmc3_dat3_pb4",
89 "sdmmc3_dat2_pb5",
90 "sdmmc3_dat1_pb6",
91 "sdmmc3_dat0_pb7",
92 "sdmmc3_dat5_pd0";
93 nvidia,function = "sdmmc3";
94 nvidia,pull = <TEGRA_PIN_PULL_UP>;
95 nvidia,tristate = <TEGRA_PIN_DISABLE>;
96 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
97 };
98
99 /* SDMMC4 pinmux */
100 sdmmc4-clk {
101 nvidia,pins = "sdmmc4_clk_pcc4";
102 nvidia,function = "sdmmc4";
103 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
105 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
106 nvidia,lock = <1>;
107 nvidia,io-reset = <1>;
108 };
109 sdmmc4-cmd {
110 nvidia,pins = "sdmmc4_cmd_pt7",
111 "sdmmc4_dat0_paa0",
112 "sdmmc4_dat1_paa1",
113 "sdmmc4_dat2_paa2",
114 "sdmmc4_dat3_paa3",
115 "sdmmc4_dat4_paa4",
116 "sdmmc4_dat5_paa5",
117 "sdmmc4_dat6_paa6",
118 "sdmmc4_dat7_paa7",
119 "sdmmc4_rst_n_pcc3";
120 nvidia,function = "sdmmc4";
121 nvidia,pull = <TEGRA_PIN_PULL_UP>;
122 nvidia,tristate = <TEGRA_PIN_DISABLE>;
123 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
124 nvidia,lock = <1>;
125 nvidia,io-reset = <1>;
126 };
127 cam-mclk {
128 nvidia,pins = "cam_mclk_pcc0";
129 nvidia,function = "vi_alt3";
130 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
131 nvidia,tristate = <TEGRA_PIN_DISABLE>;
132 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
133 };
134
135 /* I2C pinmux */
136 gen1-i2c {
137 nvidia,pins = "gen1_i2c_scl_pc4",
138 "gen1_i2c_sda_pc5";
139 nvidia,function = "i2c1";
140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
142 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
143 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
144 nvidia,lock = <0>;
145 };
146 gen2-i2c {
147 nvidia,pins = "gen2_i2c_scl_pt5",
148 "gen2_i2c_sda_pt6";
149 nvidia,function = "i2c2";
150 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
152 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
153 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
154 nvidia,lock = <0>;
155 };
156 cam-i2c {
157 nvidia,pins = "cam_i2c_scl_pbb1",
158 "cam_i2c_sda_pbb2";
159 nvidia,function = "i2c3";
160 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
161 nvidia,tristate = <TEGRA_PIN_DISABLE>;
162 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
163 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
164 nvidia,lock = <0>;
165 };
166 ddc-i2c {
167 nvidia,pins = "ddc_scl_pv4",
168 "ddc_sda_pv5";
169 nvidia,function = "i2c4";
170 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
171 nvidia,tristate = <TEGRA_PIN_DISABLE>;
172 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
173 nvidia,lock = <0>;
174 };
175 pwr-i2c {
176 nvidia,pins = "pwr_i2c_scl_pz6",
177 "pwr_i2c_sda_pz7";
178 nvidia,function = "i2cpwr";
179 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
180 nvidia,tristate = <TEGRA_PIN_DISABLE>;
181 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
182 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
183 nvidia,lock = <0>;
184 };
185
186 /* HDMI pinmux */
187 hdmi-cec {
188 nvidia,pins = "hdmi_cec_pee3";
189 nvidia,function = "cec";
190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191 nvidia,tristate = <TEGRA_PIN_DISABLE>;
192 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
193 };
194 hdmi-hpd {
195 nvidia,pins = "hdmi_int_pn7";
196 nvidia,function = "hdmi";
197 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198 nvidia,tristate = <TEGRA_PIN_DISABLE>;
199 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
200 };
201
202 /* UART-A */
203 ulpi-data0-po1 {
204 nvidia,pins = "ulpi_data0_po1";
205 nvidia,function = "uarta";
206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207 nvidia,tristate = <TEGRA_PIN_DISABLE>;
208 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
209 };
210 ulpi-data1-po2 {
211 nvidia,pins = "ulpi_data1_po2";
212 nvidia,function = "uarta";
213 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
214 nvidia,tristate = <TEGRA_PIN_ENABLE>;
215 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
216 };
217 ulpi-data2-po3 {
218 nvidia,pins = "ulpi_data2_po3",
219 "ulpi_data3_po4";
220 nvidia,function = "uarta";
221 nvidia,pull = <TEGRA_PIN_PULL_UP>;
222 nvidia,tristate = <TEGRA_PIN_DISABLE>;
223 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
224 };
225
226 /* UART-B */
227 uartb-txd-rxd {
228 nvidia,pins = "uart2_txd_pc2",
229 "uart2_rxd_pc3";
230 nvidia,function = "uartb";
231 nvidia,pull = <TEGRA_PIN_PULL_UP>;
232 nvidia,tristate = <TEGRA_PIN_ENABLE>;
233 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
234 };
235 uartb-cts-rts {
236 nvidia,pins = "uart2_cts_n_pj5",
237 "uart2_rts_n_pj6";
238 nvidia,function = "gmi";
239 nvidia,pull = <TEGRA_PIN_PULL_UP>;
240 nvidia,tristate = <TEGRA_PIN_ENABLE>;
241 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
242 };
243
244 /* UART-C */
245 uartc-rxd-cts {
246 nvidia,pins = "uart3_cts_n_pa1",
247 "uart3_rxd_pw7";
248 nvidia,function = "uartc";
249 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
250 nvidia,tristate = <TEGRA_PIN_DISABLE>;
251 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
252 };
253 uartc-txd-rts {
254 nvidia,pins = "uart3_rts_n_pc0",
255 "uart3_txd_pw6";
256 nvidia,function = "uartc";
257 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
258 nvidia,tristate = <TEGRA_PIN_DISABLE>;
259 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
260 };
261
262 /* I2S pinmux */
263 dap-i2s0-out {
264 nvidia,pins = "dap1_fs_pn0",
265 "dap1_sclk_pn3";
266 nvidia,function = "i2s0";
267 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
268 nvidia,tristate = <TEGRA_PIN_DISABLE>;
269 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
270 };
271 dap-i2s0-in {
272 nvidia,pins = "dap1_din_pn1",
273 "dap1_dout_pn2";
274 nvidia,function = "i2s0";
275 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
276 nvidia,tristate = <TEGRA_PIN_ENABLE>;
277 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
278 };
279 dap-i2s1 {
280 nvidia,pins = "dap2_fs_pa2",
281 "dap2_sclk_pa3",
282 "dap2_din_pa4",
283 "dap2_dout_pa5";
284 nvidia,function = "i2s1";
285 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
286 nvidia,tristate = <TEGRA_PIN_DISABLE>;
287 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
288 };
289 dap-i2s2 {
290 nvidia,pins = "dap3_fs_pp0",
291 "dap3_din_pp1",
292 "dap3_dout_pp2",
293 "dap3_sclk_pp3";
294 nvidia,function = "i2s2";
295 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
296 nvidia,tristate = <TEGRA_PIN_ENABLE>;
297 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
298 };
299 dap-i2s3 {
300 nvidia,pins = "dap4_fs_pp4",
301 "dap4_din_pp5",
302 "dap4_dout_pp6",
303 "dap4_sclk_pp7";
304 nvidia,function = "i2s3";
305 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
306 nvidia,tristate = <TEGRA_PIN_ENABLE>;
307 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
308 };
309 pbb0 {
310 nvidia,pins = "pbb0", "pbb7";
311 nvidia,function = "i2s4";
312 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
313 nvidia,tristate = <TEGRA_PIN_DISABLE>;
314 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
315 };
316 pcc1 {
317 nvidia,pins = "pcc1";
318 nvidia,function = "i2s4";
319 nvidia,pull = <TEGRA_PIN_PULL_UP>;
320 nvidia,tristate = <TEGRA_PIN_ENABLE>;
321 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
322 };
323 pcc2 {
324 nvidia,pins = "pcc2";
325 nvidia,function = "i2s4";
326 nvidia,pull = <TEGRA_PIN_PULL_UP>;
327 nvidia,tristate = <TEGRA_PIN_DISABLE>;
328 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
329 };
330
331 /* PCI-e pinmux */
332 pex-l2-rst-n {
333 nvidia,pins = "pex_l2_rst_n_pcc6",
334 "pex_wake_n_pdd3",
335 "pex_l1_rst_n_pdd5";
336 nvidia,function = "pcie";
337 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
338 nvidia,tristate = <TEGRA_PIN_ENABLE>;
339 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
340 };
341 pex-l2-clkreq-n {
342 nvidia,pins = "pex_l2_clkreq_n_pcc7",
343 "pex_l0_prsnt_n_pdd0",
344 "pex_l0_rst_n_pdd1",
345 "pex_l0_clkreq_n_pdd2",
346 "pex_l1_prsnt_n_pdd4",
347 "pex_l1_clkreq_n_pdd6",
348 "pex_l2_prsnt_n_pdd7";
349 nvidia,function = "pcie";
350 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
351 nvidia,tristate = <TEGRA_PIN_DISABLE>;
352 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
353 };
354
355 /* SPI pinmux */
356 spi1-miso {
357 nvidia,pins = "spi1_miso_px7";
358 nvidia,function = "spi1";
359 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
360 nvidia,tristate = <TEGRA_PIN_ENABLE>;
361 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
362 };
363 ulpi-clk {
364 nvidia,pins = "ulpi_clk_py0",
365 "ulpi_dir_py1",
366 "ulpi_nxt_py2",
367 "ulpi_stp_py3";
368 nvidia,function = "spi1";
369 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
370 nvidia,tristate = <TEGRA_PIN_ENABLE>;
371 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
372 };
373 ulpi-data7 {
374 nvidia,pins = "ulpi_data7_po0",
375 "ulpi_data4_po5",
376 "ulpi_data5_po6",
377 "ulpi_data6_po7",
378 "spi1_mosi_px4",
379 "spi1_sck_px5",
380 "spi1_cs0_n_px6";
381 nvidia,function = "spi2";
382 nvidia,pull = <TEGRA_PIN_PULL_UP>;
383 nvidia,tristate = <TEGRA_PIN_ENABLE>;
384 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
385 };
386 spi2-cs1-n {
387 nvidia,pins = "spi2_cs1_n_pw2";
388 nvidia,function = "spi3";
389 nvidia,pull = <TEGRA_PIN_PULL_UP>;
390 nvidia,tristate = <TEGRA_PIN_DISABLE>;
391 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
392 };
393 spi2-cs2-n {
394 nvidia,pins = "spi2_cs2_n_pw3";
395 nvidia,function = "spi3";
396 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
397 nvidia,tristate = <TEGRA_PIN_DISABLE>;
398 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
399 };
400 gmi-a17 {
401 nvidia,pins = "gmi_a17_pb0",
402 "gmi_a18_pb1",
403 "gmi_a16_pj7",
404 "gmi_a19_pk7";
405 nvidia,function = "spi4";
406 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
407 nvidia,tristate = <TEGRA_PIN_DISABLE>;
408 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
409 };
410 spi2-sck {
411 nvidia,pins = "spi2_sck_px2";
412 nvidia,function = "spi6";
413 nvidia,pull = <TEGRA_PIN_PULL_UP>;
414 nvidia,tristate = <TEGRA_PIN_DISABLE>;
415 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
416 };
417
418 /* Display A pinmux */
419 lcd-pclk {
420 nvidia,pins = "lcd_pclk_pb3",
421 "lcd_dc1_pd2",
422 "lcd_d0_pe0",
423 "lcd_d1_pe1",
424 "lcd_d2_pe2",
425 "lcd_d3_pe3",
426 "lcd_d4_pe4",
427 "lcd_d5_pe5",
428 "lcd_d6_pe6",
429 "lcd_d7_pe7",
430 "lcd_d8_pf0",
431 "lcd_d9_pf1",
432 "lcd_d10_pf2",
433 "lcd_d11_pf3",
434 "lcd_d12_pf4",
435 "lcd_d13_pf5",
436 "lcd_d14_pf6",
437 "lcd_d15_pf7",
438 "lcd_de_pj1",
439 "lcd_d16_pm0",
440 "lcd_d17_pm1",
441 "lcd_d18_pm2",
442 "lcd_d19_pm3",
443 "lcd_d20_pm4",
444 "lcd_d21_pm5",
445 "lcd_d22_pm6",
446 "lcd_d23_pm7",
447 "lcd_sdout_pn5",
448 "lcd_dc0_pn6",
449 "lcd_m1_pw1",
450 "lcd_sdin_pz2",
451 "lcd_sck_pz4";
452 nvidia,function = "displaya";
453 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
454 nvidia,tristate = <TEGRA_PIN_DISABLE>;
455 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
456 };
457 lcd-pwr1 {
458 nvidia,pins = "lcd_pwr1_pc1",
459 "lcd_pwr2_pc6";
460 nvidia,function = "displaya";
461 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
462 nvidia,tristate = <TEGRA_PIN_ENABLE>;
463 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
464 };
465 lcd-hsync {
466 nvidia,pins = "lcd_hsync_pj3",
467 "lcd_vsync_pj4",
468 "lcd_cs0_n_pn4",
469 "lcd_cs1_n_pw0",
470 "lcd_wr_n_pz3";
471 nvidia,function = "displaya";
472 nvidia,pull = <TEGRA_PIN_PULL_UP>;
473 nvidia,tristate = <TEGRA_PIN_DISABLE>;
474 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
475 };
476 lcd-pwr0 {
477 nvidia,pins = "lcd_pwr0_pb2";
478 nvidia,function = "displaya";
479 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
480 nvidia,tristate = <TEGRA_PIN_DISABLE>;
481 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
482 };
483 crt-hsync-pv6 {
484 nvidia,pins = "crt_hsync_pv6",
485 "crt_vsync_pv7";
486 nvidia,function = "crt";
487 nvidia,pull = <TEGRA_PIN_PULL_UP>;
488 nvidia,tristate = <TEGRA_PIN_ENABLE>;
489 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
490 };
491
492 blink {
493 nvidia,pins = "clk_32k_out_pa0";
494 nvidia,function = "blink";
495 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
496 nvidia,tristate = <TEGRA_PIN_DISABLE>;
497 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
498 };
499
500 /* KBC keys */
501 kb-col0 {
502 nvidia,pins = "kb_col0_pq0",
503 "kb_col1_pq1",
504 "kb_col2_pq2",
505 "kb_col3_pq3",
506 "kb_col4_pq4",
507 "kb_col5_pq5",
508 "kb_col6_pq6",
509 "kb_col7_pq7",
510 "kb_row12_ps4";
511 nvidia,function = "kbc";
512 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
513 nvidia,tristate = <TEGRA_PIN_ENABLE>;
514 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
515 };
516 kb-row0 {
517 nvidia,pins = "kb_row0_pr0",
518 "kb_row1_pr1",
519 "kb_row5_pr5";
520 nvidia,function = "kbc";
521 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
522 nvidia,tristate = <TEGRA_PIN_DISABLE>;
523 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
524 };
525 kb-row2 {
526 nvidia,pins = "kb_row2_pr2",
527 "kb_row3_pr3",
528 "kb_row6_pr6",
529 "kb_row7_pr7",
530 "kb_row11_ps3";
531 nvidia,function = "kbc";
532 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
533 nvidia,tristate = <TEGRA_PIN_DISABLE>;
534 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
535 };
536 kb-row4 {
537 nvidia,pins = "kb_row4_pr4",
538 "kb_row9_ps1";
539 nvidia,function = "kbc";
540 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
541 nvidia,tristate = <TEGRA_PIN_ENABLE>;
542 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
543 };
544 kb-row8 {
545 nvidia,pins = "kb_row8_ps0",
546 "kb_row10_ps2";
547 nvidia,function = "kbc";
548 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
549 nvidia,tristate = <TEGRA_PIN_DISABLE>;
550 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
551 };
552 kb-row13 {
553 nvidia,pins = "kb_row13_ps5",
554 "kb_row14_ps6",
555 "kb_row15_ps7";
556 nvidia,function = "kbc";
557 nvidia,pull = <TEGRA_PIN_PULL_UP>;
558 nvidia,tristate = <TEGRA_PIN_DISABLE>;
559 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
560 };
561
562 /* SPDIF pinmux */
563 spdif-pins {
564 nvidia,pins = "spdif_out_pk5",
565 "spdif_in_pk6";
566 nvidia,function = "spdif";
567 nvidia,pull = <TEGRA_PIN_PULL_UP>;
568 nvidia,tristate = <TEGRA_PIN_ENABLE>;
569 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
570 };
571 sdmmc3-dat6 {
572 nvidia,pins = "sdmmc3_dat6_pd3",
573 "sdmmc3_dat7_pd4";
574 nvidia,function = "spdif";
575 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
576 nvidia,tristate = <TEGRA_PIN_ENABLE>;
577 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
578 };
579
580 jtag-rtck {
581 nvidia,pins = "jtag_rtck_pu7";
582 nvidia,function = "rtck";
583 nvidia,pull = <TEGRA_PIN_PULL_UP>;
584 nvidia,tristate = <TEGRA_PIN_DISABLE>;
585 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
586 };
587
588 /* GMI pinmux */
589 gmi-wp-n {
590 nvidia,pins = "gmi_wp_n_pc7",
591 "gmi_cs7_n_pi6";
592 nvidia,function = "gmi";
593 nvidia,pull = <TEGRA_PIN_PULL_UP>;
594 nvidia,tristate = <TEGRA_PIN_ENABLE>;
595 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
596 };
597 sdmmc3-dat4 {
598 nvidia,pins = "sdmmc3_dat4_pd1",
599 "gmi_ad9_ph1";
600 nvidia,function = "pwm1";
601 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
602 nvidia,tristate = <TEGRA_PIN_DISABLE>;
603 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
604 };
605 gmi-ad0-pg0 {
606 nvidia,pins = "gmi_ad0_pg0",
607 "gmi_ad1_pg1",
608 "gmi_ad2_pg2",
609 "gmi_ad3_pg3",
610 "gmi_ad4_pg4",
611 "gmi_ad5_pg5",
612 "gmi_ad6_pg6",
613 "gmi_ad7_pg7",
614 "gmi_ad15_ph7";
615 nvidia,function = "gmi";
616 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
617 nvidia,tristate = <TEGRA_PIN_ENABLE>;
618 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
619 };
620 gmi-ad8 {
621 nvidia,pins = "gmi_ad8_ph0";
622 nvidia,function = "pwm0";
623 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
624 nvidia,tristate = <TEGRA_PIN_DISABLE>;
625 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
626 };
627 gmi-ad10 {
628 nvidia,pins = "gmi_ad10_ph2",
629 "gmi_ad11_ph3";
630 nvidia,function = "gmi";
631 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
632 nvidia,tristate = <TEGRA_PIN_ENABLE>;
633 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
634 };
635 gmi-ad12 {
636 nvidia,pins = "gmi_ad12_ph4",
637 "gmi_ad13_ph5",
638 "gmi_iordy_pi5",
639 "gmi_cs0_n_pj0",
640 "pu1",
641 "pu2",
642 "pv1",
643 "pv2",
644 "pv3";
645 nvidia,function = "rsvd1";
646 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
647 nvidia,tristate = <TEGRA_PIN_ENABLE>;
648 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
649 };
650 gmi-wr-n {
651 nvidia,pins = "gmi_wr_n_pi0",
652 "gmi_oe_n_pi1",
653 "gmi_adv_n_pk0",
654 "gmi_clk_pk1";
655 nvidia,function = "gmi";
656 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
657 nvidia,tristate = <TEGRA_PIN_DISABLE>;
658 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
659 };
660 gmi-dqs {
661 nvidia,pins = "gmi_dqs_pi2";
662 nvidia,function = "rsvd1";
663 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
664 nvidia,tristate = <TEGRA_PIN_DISABLE>;
665 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
666 };
667 gmi-wait {
668 nvidia,pins = "gmi_wait_pi7",
669 "gmi_cs2_n_pk3",
670 "gmi_cs3_n_pk4";
671 nvidia,function = "gmi";
672 nvidia,pull = <TEGRA_PIN_PULL_UP>;
673 nvidia,tristate = <TEGRA_PIN_DISABLE>;
674 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
675 };
676 gmi-cs4-n {
677 nvidia,pins = "gmi_cs4_n_pk2";
678 nvidia,function = "rsvd1";
679 nvidia,pull = <TEGRA_PIN_PULL_UP>;
680 nvidia,tristate = <TEGRA_PIN_ENABLE>;
681 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
682 };
683 gmi-ad14-ph6 {
684 nvidia,pins = "gmi_ad14_ph6";
685 nvidia,function = "rsvd1";
686 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
687 nvidia,tristate = <TEGRA_PIN_DISABLE>;
688 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
689 };
690
691 /* VI pinmux */
692 vi-d1-pd5 {
693 nvidia,pins = "vi_d1_pd5",
694 "vi_vsync_pd6",
695 "vi_d2_pl0",
696 "vi_d4_pl2",
697 "vi_d5_pl3",
698 "vi_d6_pl4",
699 "vi_pclk_pt0",
700 "vi_d10_pt2",
701 "vi_d0_pt4";
702 nvidia,function = "rsvd1";
703 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
704 nvidia,tristate = <TEGRA_PIN_ENABLE>;
705 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
706 nvidia,lock = <1>;
707 nvidia,io-reset = <1>;
708 };
709 vi-d3-pl1 {
710 nvidia,pins = "vi_d3_pl1";
711 nvidia,function = "rsvd1";
712 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
713 nvidia,tristate = <TEGRA_PIN_ENABLE>;
714 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
715 nvidia,lock = <1>;
716 nvidia,io-reset = <1>;
717 };
718 vi-hsync-pd7 {
719 nvidia,pins = "vi_hsync_pd7",
720 "vi_d7_pl5",
721 "vi_d8_pl6",
722 "vi_d9_pl7";
723 nvidia,function = "rsvd1";
724 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
725 nvidia,tristate = <TEGRA_PIN_DISABLE>;
726 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
727 nvidia,lock = <1>;
728 nvidia,io-reset = <1>;
729 };
730 vi-mclk-pt1 {
731 nvidia,pins = "vi_mclk_pt1";
732 nvidia,function = "vi";
733 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
734 nvidia,tristate = <TEGRA_PIN_ENABLE>;
735 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
736 nvidia,lock = <1>;
737 nvidia,io-reset = <1>;
738 };
739 vi-d11-pt3 {
740 nvidia,pins = "vi_d11_pt3";
741 nvidia,function = "ddr";
742 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
743 nvidia,tristate = <TEGRA_PIN_DISABLE>;
744 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
745 nvidia,lock = <1>;
746 nvidia,io-reset = <1>;
747 };
748
749 /* PORT U */
750 pu0 {
751 nvidia,pins = "pu0";
752 nvidia,function = "owr";
753 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
754 nvidia,tristate = <TEGRA_PIN_ENABLE>;
755 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
756 };
757 pu3 {
758 nvidia,pins = "pu3";
759 nvidia,function = "pwm0";
760 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
761 nvidia,tristate = <TEGRA_PIN_ENABLE>;
762 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
763 };
764 pu4 {
765 nvidia,pins = "pu4";
766 nvidia,function = "pwm1";
767 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
768 nvidia,tristate = <TEGRA_PIN_ENABLE>;
769 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
770 };
771 pu5 {
772 nvidia,pins = "pu5";
773 nvidia,function = "pwm2";
774 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
775 nvidia,tristate = <TEGRA_PIN_ENABLE>;
776 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
777 };
778 pu6 {
779 nvidia,pins = "pu6";
780 nvidia,function = "pwm3";
781 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
782 nvidia,tristate = <TEGRA_PIN_ENABLE>;
783 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
784 };
785
786 /* PORT V */
787 pv0 {
788 nvidia,pins = "pv0";
789 nvidia,function = "rsvd1";
790 nvidia,pull = <TEGRA_PIN_PULL_UP>;
791 nvidia,tristate = <TEGRA_PIN_DISABLE>;
792 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
793 };
794
795 /* PORT BB */
796 pbb3 {
797 nvidia,pins = "pbb3";
798 nvidia,function = "vgp3";
799 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
800 nvidia,tristate = <TEGRA_PIN_ENABLE>;
801 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
802 };
803 pbb4 {
804 nvidia,pins = "pbb4";
805 nvidia,function = "vgp4";
806 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
807 nvidia,tristate = <TEGRA_PIN_DISABLE>;
808 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
809 };
810 pbb5 {
811 nvidia,pins = "pbb5";
812 nvidia,function = "vgp5";
813 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
814 nvidia,tristate = <TEGRA_PIN_ENABLE>;
815 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
816 };
817 pbb6 {
818 nvidia,pins = "pbb6";
819 nvidia,function = "vgp6";
820 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
821 nvidia,tristate = <TEGRA_PIN_DISABLE>;
822 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
823 };
824
825 /* CLK pinmux */
826 clk1-out-pw4 {
827 nvidia,pins = "clk1_out_pw4";
828 nvidia,function = "extperiph1";
829 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
830 nvidia,tristate = <TEGRA_PIN_DISABLE>;
831 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
832 };
833 clk2-out-pw5 {
834 nvidia,pins = "clk2_out_pw5";
835 nvidia,function = "extperiph2";
836 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
837 nvidia,tristate = <TEGRA_PIN_ENABLE>;
838 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
839 };
840 clk2-req-pcc5 {
841 nvidia,pins = "clk2_req_pcc5",
842 "clk1_req_pee2";
843 nvidia,function = "dap";
844 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
845 nvidia,tristate = <TEGRA_PIN_ENABLE>;
846 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
847 };
848 clk3-out-pee0 {
849 nvidia,pins = "clk3_out_pee0";
850 nvidia,function = "extperiph3";
851 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
852 nvidia,tristate = <TEGRA_PIN_DISABLE>;
853 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
854 };
855 clk3-req-pee1 {
856 nvidia,pins = "clk3_req_pee1";
857 nvidia,function = "dev3";
858 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
859 nvidia,tristate = <TEGRA_PIN_DISABLE>;
860 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
861 };
862 sys-clk-req-pz5 {
863 nvidia,pins = "sys_clk_req_pz5";
864 nvidia,function = "sysclk";
865 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
866 nvidia,tristate = <TEGRA_PIN_DISABLE>;
867 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
868 };
869
870 owr {
871 nvidia,pins = "owr";
872 nvidia,function = "owr";
873 nvidia,pull = <TEGRA_PIN_PULL_UP>;
874 nvidia,tristate = <TEGRA_PIN_DISABLE>;
875 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
876 };
877
878 /* GPIO power/drive control */
879 drive-sdio1 {
880 nvidia,pins = "drive_sdio1",
881 "drive_sdio3";
882 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
883 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
884 nvidia,pull-down-strength = <46>;
885 nvidia,pull-up-strength = <42>;
886 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
887 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
888 };
889 };
890 };
891
892 uarta: serial@70006000 {
893 status = "okay";
894 };
895
896 pwm: pwm@7000a000 {
897 status = "okay";
898 };
899
900 pwr_i2c: i2c@7000d000 {
901 status = "okay";
902 clock-frequency = <400000>;
903
904 /* Texas Instruments TPS659110 PMIC */
905 pmic: tps65911@2d {
906 compatible = "ti,tps65911";
907 reg = <0x2d>;
908
909 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
910 #interrupt-cells = <2>;
911 interrupt-controller;
912
913 ti,system-power-controller;
914
915 #gpio-cells = <2>;
916 gpio-controller;
917
918 regulators {
919 vdd_1v8_vio: vddio {
920 regulator-name = "vdd_1v8_gen";
921 regulator-min-microvolt = <1800000>;
922 regulator-max-microvolt = <1800000>;
923 regulator-always-on;
924 regulator-boot-on;
925 };
926
927 vddio_usd: ldo5 {
928 regulator-name = "vddio_usd";
929 regulator-min-microvolt = <3300000>;
930 regulator-max-microvolt = <3300000>;
931 regulator-always-on;
932 regulator-boot-on;
933 };
934 };
935 };
936 };
937
938 spi4: spi@7000da00 {
939 status = "okay";
940 spi-max-frequency = <25000000>;
941
942 spi-flash@1 {
943 compatible = "winbond,w25q32", "jedec,spi-nor";
944 reg = <1>;
945 spi-max-frequency = <20000000>;
946 };
947 };
948
949 sdmmc1: sdhci@78000000 {
950 status = "okay";
951 bus-width = <4>;
952
953 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
954
955 vmmc-supply = <&vdd_usd>;
956 vqmmc-supply = <&vddio_usd>;
957 };
958
959 sdmmc4: sdhci@78000600 {
960 status = "okay";
961 bus-width = <8>;
962 non-removable;
963
964 vmmc-supply = <&vdd_3v3_sys>;
965 vqmmc-supply = <&vdd_1v8_vio>;
966 };
967
968 /* Main USB port */
969 usb1: usb@7d000000 {
970 status = "okay";
971 dr_mode = "otg";
972 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
973 };
974
975 backlight: backlight {
976 compatible = "pwm-backlight";
977
978 enable-gpios = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
979 pwms = <&pwm 0 50000>;
980
981 brightness-levels = <1 35 70 105 140 175 210 255>;
982 default-brightness-level = <5>;
983 };
984
985 /* PMIC has a built-in 32KHz oscillator which is used by PMC */
986 clk32k_in: clock-32k {
987 compatible = "fixed-clock";
988 #clock-cells = <0>;
989 clock-frequency = <32768>;
990 clock-output-names = "pmic-oscillator";
991 };
992
993 extcon-keys {
994 compatible = "gpio-keys";
995
996 switch-hall-sensor {
997 label = "Hall Sensor";
998 gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
999 linux,code = <SW_LID>;
1000 };
1001 };
1002
1003 gpio-keys {
1004 compatible = "gpio-keys";
1005
1006 key-power {
1007 label = "Power";
1008 gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
1009 linux,code = <KEY_CANCEL>;
1010 };
1011
1012 key-volume-down {
1013 label = "Volume Down";
1014 gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
1015 linux,code = <KEY_DOWN>;
1016 };
1017
1018 key-volume-up {
1019 label = "Volume Up";
1020 gpios = <&gpio TEGRA_GPIO(S, 7) GPIO_ACTIVE_LOW>;
1021 linux,code = <KEY_UP>;
1022 };
1023
1024 key-windows-button {
1025 label = "Windows Button";
1026 gpios = <&gpio TEGRA_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
1027 linux,code = <KEY_ENTER>;
1028 };
1029 };
1030
1031 panel: panel {
1032 compatible = "simple-panel";
1033
1034 power-supply = <&vdd_pnl_reg>;
1035 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
1036
1037 backlight = <&backlight>;
1038
1039 display-timings {
1040 timing@0 {
1041 /* 1366x768@60Hz */
1042 clock-frequency = <71980000>;
1043
1044 hactive = <1366>;
1045 hfront-porch = <56>;
1046 hback-porch = <106>;
1047 hsync-len = <14>;
1048
1049 vactive = <768>;
1050 vfront-porch = <3>;
1051 vback-porch = <6>;
1052 vsync-len = <1>;
1053 };
1054 };
1055 };
1056
1057 vdd_3v3_sys: regulator-3v {
1058 compatible = "regulator-fixed";
1059 regulator-name = "vdd_3v3_sys";
1060 regulator-min-microvolt = <3300000>;
1061 regulator-max-microvolt = <3300000>;
1062 regulator-always-on;
1063 regulator-boot-on;
1064 };
1065
1066 vdd_usd: regulator-usd {
1067 compatible = "regulator-fixed";
1068 regulator-name = "vdd_usd";
1069 regulator-min-microvolt = <3300000>;
1070 regulator-max-microvolt = <3300000>;
1071 gpio = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
1072 enable-active-high;
1073 };
1074
1075 vdd_pnl_reg: regulator-pnl {
1076 compatible = "regulator-fixed";
1077 regulator-name = "vdd_panel";
1078 regulator-min-microvolt = <3300000>;
1079 regulator-max-microvolt = <3300000>;
1080 gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
1081 enable-active-high;
1082 };
1083};