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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChung Liewb354aef2009-06-12 11:29:00 +00002/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Alison Wang95bed1f2012-03-26 21:49:04 +00006 * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
TsiChung Liewb354aef2009-06-12 11:29:00 +00007 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewb354aef2009-06-12 11:29:00 +00008 */
9
10#include <config.h>
11#include <common.h>
12#include <asm/immap.h>
Alison Wang95bed1f2012-03-26 21:49:04 +000013#include <asm/io.h>
TsiChung Liewb354aef2009-06-12 11:29:00 +000014
15DECLARE_GLOBAL_DATA_PTR;
16
17int checkboard(void)
18{
19 puts("Board: ");
20 puts("Freescale M5208EVBe\n");
21 return 0;
22};
23
Simon Glassd35f3382017-04-06 12:47:05 -060024int dram_init(void)
TsiChung Liewb354aef2009-06-12 11:29:00 +000025{
Alison Wang95bed1f2012-03-26 21:49:04 +000026 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
TsiChung Liewb354aef2009-06-12 11:29:00 +000027 u32 dramsize, i;
28
29 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
30
31 for (i = 0x13; i < 0x20; i++) {
32 if (dramsize == (1 << i))
33 break;
34 }
35 i--;
36
Alison Wang95bed1f2012-03-26 21:49:04 +000037 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
TsiChung Liewb354aef2009-06-12 11:29:00 +000038#ifdef CONFIG_SYS_SDRAM_BASE1
Alison Wang95bed1f2012-03-26 21:49:04 +000039 out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
TsiChung Liewb354aef2009-06-12 11:29:00 +000040#endif
Alison Wang95bed1f2012-03-26 21:49:04 +000041 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
42 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
TsiChung Liewb354aef2009-06-12 11:29:00 +000043
44 udelay(500);
45
46 /* Issue PALL */
Alison Wang95bed1f2012-03-26 21:49:04 +000047 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
TsiChung Liewb354aef2009-06-12 11:29:00 +000048 asm("nop");
49
50 /* Perform two refresh cycles */
Alison Wang95bed1f2012-03-26 21:49:04 +000051 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
52 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
TsiChung Liewb354aef2009-06-12 11:29:00 +000053 asm("nop");
54
55 /* Issue LEMR */
Alison Wang95bed1f2012-03-26 21:49:04 +000056 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
TsiChung Liewb354aef2009-06-12 11:29:00 +000057 asm("nop");
Alison Wang95bed1f2012-03-26 21:49:04 +000058 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
TsiChung Liewb354aef2009-06-12 11:29:00 +000059 asm("nop");
60
Alison Wang95bed1f2012-03-26 21:49:04 +000061 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
TsiChung Liewb354aef2009-06-12 11:29:00 +000062 asm("nop");
63
Alison Wang95bed1f2012-03-26 21:49:04 +000064 out_be32(&sdram->ctrl,
65 (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
TsiChung Liewb354aef2009-06-12 11:29:00 +000066 asm("nop");
67
68 udelay(100);
69
Simon Glass39f90ba2017-03-31 08:40:25 -060070 gd->ram_size = dramsize;
71
72 return 0;
TsiChung Liewb354aef2009-06-12 11:29:00 +000073};
74
75int testdram(void)
76{
77 /* TODO: XXX XXX XXX */
78 printf("DRAM test not implemented!\n");
79
80 return (0);
81}