Alison Wang | 695c9b5 | 2013-05-27 22:55:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 3 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Alison Wang | 695c9b5 | 2013-05-27 22:55:47 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
| 9 | #include <asm/arch/imx-regs.h> |
| 10 | #include <asm/arch/iomux-vf610.h> |
| 11 | #include <asm/arch/crm_regs.h> |
| 12 | #include <asm/arch/clock.h> |
| 13 | #include <mmc.h> |
| 14 | #include <fsl_esdhc.h> |
| 15 | #include <miiphy.h> |
| 16 | #include <netdev.h> |
Alison Wang | 86bef20 | 2013-06-17 15:30:38 +0800 | [diff] [blame] | 17 | #include <i2c.h> |
Alison Wang | 695c9b5 | 2013-05-27 22:55:47 +0000 | [diff] [blame] | 18 | |
| 19 | DECLARE_GLOBAL_DATA_PTR; |
| 20 | |
| 21 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| 22 | PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) |
| 23 | |
| 24 | #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ |
| 25 | PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) |
| 26 | |
| 27 | #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ |
| 28 | PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) |
| 29 | |
| 30 | void setup_iomux_ddr(void) |
| 31 | { |
| 32 | static const iomux_v3_cfg_t ddr_pads[] = { |
| 33 | VF610_PAD_DDR_A15__DDR_A_15, |
| 34 | VF610_PAD_DDR_A15__DDR_A_15, |
| 35 | VF610_PAD_DDR_A14__DDR_A_14, |
| 36 | VF610_PAD_DDR_A13__DDR_A_13, |
| 37 | VF610_PAD_DDR_A12__DDR_A_12, |
| 38 | VF610_PAD_DDR_A11__DDR_A_11, |
| 39 | VF610_PAD_DDR_A10__DDR_A_10, |
| 40 | VF610_PAD_DDR_A9__DDR_A_9, |
| 41 | VF610_PAD_DDR_A8__DDR_A_8, |
| 42 | VF610_PAD_DDR_A7__DDR_A_7, |
| 43 | VF610_PAD_DDR_A6__DDR_A_6, |
| 44 | VF610_PAD_DDR_A5__DDR_A_5, |
| 45 | VF610_PAD_DDR_A4__DDR_A_4, |
| 46 | VF610_PAD_DDR_A3__DDR_A_3, |
| 47 | VF610_PAD_DDR_A2__DDR_A_2, |
| 48 | VF610_PAD_DDR_A1__DDR_A_1, |
| 49 | VF610_PAD_DDR_BA2__DDR_BA_2, |
| 50 | VF610_PAD_DDR_BA1__DDR_BA_1, |
| 51 | VF610_PAD_DDR_BA0__DDR_BA_0, |
| 52 | VF610_PAD_DDR_CAS__DDR_CAS_B, |
| 53 | VF610_PAD_DDR_CKE__DDR_CKE_0, |
| 54 | VF610_PAD_DDR_CLK__DDR_CLK_0, |
| 55 | VF610_PAD_DDR_CS__DDR_CS_B_0, |
| 56 | VF610_PAD_DDR_D15__DDR_D_15, |
| 57 | VF610_PAD_DDR_D14__DDR_D_14, |
| 58 | VF610_PAD_DDR_D13__DDR_D_13, |
| 59 | VF610_PAD_DDR_D12__DDR_D_12, |
| 60 | VF610_PAD_DDR_D11__DDR_D_11, |
| 61 | VF610_PAD_DDR_D10__DDR_D_10, |
| 62 | VF610_PAD_DDR_D9__DDR_D_9, |
| 63 | VF610_PAD_DDR_D8__DDR_D_8, |
| 64 | VF610_PAD_DDR_D7__DDR_D_7, |
| 65 | VF610_PAD_DDR_D6__DDR_D_6, |
| 66 | VF610_PAD_DDR_D5__DDR_D_5, |
| 67 | VF610_PAD_DDR_D4__DDR_D_4, |
| 68 | VF610_PAD_DDR_D3__DDR_D_3, |
| 69 | VF610_PAD_DDR_D2__DDR_D_2, |
| 70 | VF610_PAD_DDR_D1__DDR_D_1, |
| 71 | VF610_PAD_DDR_D0__DDR_D_0, |
| 72 | VF610_PAD_DDR_DQM1__DDR_DQM_1, |
| 73 | VF610_PAD_DDR_DQM0__DDR_DQM_0, |
| 74 | VF610_PAD_DDR_DQS1__DDR_DQS_1, |
| 75 | VF610_PAD_DDR_DQS0__DDR_DQS_0, |
| 76 | VF610_PAD_DDR_RAS__DDR_RAS_B, |
| 77 | VF610_PAD_DDR_WE__DDR_WE_B, |
| 78 | VF610_PAD_DDR_ODT1__DDR_ODT_0, |
| 79 | VF610_PAD_DDR_ODT0__DDR_ODT_1, |
| 80 | }; |
| 81 | |
| 82 | imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); |
| 83 | } |
| 84 | |
| 85 | void ddr_phy_init(void) |
| 86 | { |
| 87 | struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; |
| 88 | |
| 89 | writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]); |
| 90 | writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]); |
| 91 | writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]); |
| 92 | writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]); |
| 93 | |
| 94 | writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]); |
| 95 | writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]); |
| 96 | writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]); |
| 97 | writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]); |
| 98 | |
| 99 | writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]); |
| 100 | writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]); |
| 101 | writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]); |
| 102 | writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]); |
| 103 | |
| 104 | writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]); |
| 105 | writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]); |
| 106 | writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]); |
| 107 | writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]); |
| 108 | |
| 109 | writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]); |
| 110 | writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]); |
| 111 | writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]); |
| 112 | writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]); |
| 113 | |
| 114 | writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, |
| 115 | &ddrmr->phy[50]); |
| 116 | } |
| 117 | |
| 118 | void ddr_ctrl_init(void) |
| 119 | { |
| 120 | struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; |
| 121 | |
| 122 | writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); |
| 123 | writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]); |
| 124 | writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]); |
| 125 | |
| 126 | writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]); |
| 127 | writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]); |
| 128 | writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) | |
| 129 | DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]); |
| 130 | writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) | |
| 131 | DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]); |
| 132 | writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]); |
| 133 | writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12), |
| 134 | &ddrmr->cr[17]); |
| 135 | writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]); |
| 136 | |
| 137 | writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); |
| 138 | writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT | |
| 139 | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); |
| 140 | |
| 141 | writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]); |
| 142 | writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]); |
| 143 | writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]); |
| 144 | |
| 145 | writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); |
| 146 | writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); |
| 147 | writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]); |
| 148 | writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]); |
| 149 | |
| 150 | writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]); |
| 151 | writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]); |
| 152 | writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); |
| 153 | writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]); |
| 154 | |
| 155 | writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]); |
| 156 | writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | |
| 157 | DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]); |
| 158 | |
| 159 | writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]); |
| 160 | writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056), |
| 161 | &ddrmr->cr[48]); |
| 162 | |
| 163 | writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]); |
| 164 | writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]); |
| 165 | writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]); |
| 166 | |
| 167 | writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]); |
| 168 | writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]); |
| 169 | |
| 170 | writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) | |
| 171 | DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]); |
| 172 | writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN | |
| 173 | DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255), |
| 174 | &ddrmr->cr[74]); |
| 175 | writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN | |
| 176 | DDRMC_CR75_PLEN, &ddrmr->cr[75]); |
| 177 | writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) | |
| 178 | DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]); |
| 179 | writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE | |
| 180 | DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); |
| 181 | writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); |
| 182 | writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]); |
| 183 | |
| 184 | writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); |
| 185 | |
| 186 | writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0, |
| 187 | &ddrmr->cr[87]); |
| 188 | writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); |
| 189 | writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]); |
| 190 | |
| 191 | writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); |
| 192 | writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]); |
| 193 | |
| 194 | writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]); |
| 195 | writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]); |
| 196 | writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]); |
| 197 | |
| 198 | writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), |
| 199 | &ddrmr->cr[117]); |
| 200 | writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), |
| 201 | &ddrmr->cr[118]); |
| 202 | |
| 203 | writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2), |
| 204 | &ddrmr->cr[120]); |
| 205 | writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2), |
| 206 | &ddrmr->cr[121]); |
| 207 | writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | |
| 208 | DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]); |
| 209 | writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1), |
| 210 | &ddrmr->cr[123]); |
| 211 | writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]); |
| 212 | |
| 213 | writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]); |
| 214 | writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), |
| 215 | &ddrmr->cr[132]); |
| 216 | writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | |
| 217 | DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3), |
| 218 | &ddrmr->cr[139]); |
| 219 | |
| 220 | writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | |
| 221 | DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]); |
| 222 | writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2), |
| 223 | &ddrmr->cr[155]); |
| 224 | writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); |
| 225 | |
| 226 | ddr_phy_init(); |
| 227 | |
| 228 | writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); |
| 229 | |
| 230 | udelay(200); |
| 231 | } |
| 232 | |
| 233 | int dram_init(void) |
| 234 | { |
| 235 | setup_iomux_ddr(); |
| 236 | |
| 237 | ddr_ctrl_init(); |
| 238 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
| 239 | |
| 240 | return 0; |
| 241 | } |
| 242 | |
| 243 | static void setup_iomux_uart(void) |
| 244 | { |
| 245 | static const iomux_v3_cfg_t uart1_pads[] = { |
| 246 | NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), |
| 247 | NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), |
| 248 | }; |
| 249 | |
| 250 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 251 | } |
| 252 | |
| 253 | static void setup_iomux_enet(void) |
| 254 | { |
| 255 | static const iomux_v3_cfg_t enet0_pads[] = { |
| 256 | NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), |
| 257 | NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), |
| 258 | NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), |
| 259 | NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), |
| 260 | NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), |
| 261 | NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), |
| 262 | NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), |
| 263 | NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), |
| 264 | NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), |
| 265 | NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), |
| 266 | }; |
| 267 | |
| 268 | imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); |
| 269 | } |
| 270 | |
Alison Wang | 86bef20 | 2013-06-17 15:30:38 +0800 | [diff] [blame] | 271 | static void setup_iomux_i2c(void) |
| 272 | { |
| 273 | static const iomux_v3_cfg_t i2c0_pads[] = { |
| 274 | VF610_PAD_PTB14__I2C0_SCL, |
| 275 | VF610_PAD_PTB15__I2C0_SDA, |
| 276 | }; |
| 277 | |
| 278 | imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); |
| 279 | } |
| 280 | |
Alison Wang | 695c9b5 | 2013-05-27 22:55:47 +0000 | [diff] [blame] | 281 | #ifdef CONFIG_FSL_ESDHC |
| 282 | struct fsl_esdhc_cfg esdhc_cfg[1] = { |
| 283 | {ESDHC1_BASE_ADDR}, |
| 284 | }; |
| 285 | |
| 286 | int board_mmc_getcd(struct mmc *mmc) |
| 287 | { |
| 288 | /* eSDHC1 is always present */ |
| 289 | return 1; |
| 290 | } |
| 291 | |
| 292 | int board_mmc_init(bd_t *bis) |
| 293 | { |
| 294 | static const iomux_v3_cfg_t esdhc1_pads[] = { |
| 295 | NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), |
| 296 | NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), |
| 297 | NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), |
| 298 | NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), |
| 299 | NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), |
| 300 | NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), |
| 301 | }; |
Alison Wang | 695c9b5 | 2013-05-27 22:55:47 +0000 | [diff] [blame] | 302 | |
| 303 | esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
| 304 | |
| 305 | imx_iomux_v3_setup_multiple_pads( |
| 306 | esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); |
| 307 | |
Fabio Estevam | a03908e | 2013-06-05 11:34:48 +0000 | [diff] [blame] | 308 | return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); |
Alison Wang | 695c9b5 | 2013-05-27 22:55:47 +0000 | [diff] [blame] | 309 | } |
| 310 | #endif |
| 311 | |
| 312 | static void clock_init(void) |
| 313 | { |
| 314 | struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; |
| 315 | struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; |
| 316 | |
| 317 | clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, |
| 318 | CCM_CCGR0_UART1_CTRL_MASK); |
| 319 | clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, |
| 320 | CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); |
| 321 | clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, |
| 322 | CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | |
| 323 | CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | |
| 324 | CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK); |
| 325 | clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, |
| 326 | CCM_CCGR3_ANADIG_CTRL_MASK); |
| 327 | clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, |
| 328 | CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | |
Alison Wang | 86bef20 | 2013-06-17 15:30:38 +0800 | [diff] [blame] | 329 | CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); |
Alison Wang | 695c9b5 | 2013-05-27 22:55:47 +0000 | [diff] [blame] | 330 | clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, |
| 331 | CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); |
| 332 | clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, |
| 333 | CCM_CCGR7_SDHC1_CTRL_MASK); |
| 334 | clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, |
| 335 | CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); |
| 336 | |
| 337 | clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, |
| 338 | ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); |
| 339 | clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, |
| 340 | ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); |
| 341 | |
| 342 | clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, |
| 343 | CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); |
| 344 | clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, |
| 345 | CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | |
| 346 | CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | |
| 347 | CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | |
| 348 | CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | |
| 349 | CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | |
| 350 | CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); |
| 351 | clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, |
| 352 | CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | |
| 353 | CCM_CACRR_ARM_CLK_DIV(0)); |
| 354 | clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, |
| 355 | CCM_CSCMR1_ESDHC1_CLK_SEL(3)); |
| 356 | clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, |
| 357 | CCM_CSCDR1_RMII_CLK_EN); |
| 358 | clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, |
| 359 | CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0)); |
| 360 | clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, |
| 361 | CCM_CSCMR2_RMII_CLK_SEL(0)); |
| 362 | } |
| 363 | |
| 364 | static void mscm_init(void) |
| 365 | { |
| 366 | struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; |
| 367 | int i; |
| 368 | |
| 369 | for (i = 0; i < MSCM_IRSPRC_NUM; i++) |
| 370 | writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); |
| 371 | } |
| 372 | |
| 373 | int board_phy_config(struct phy_device *phydev) |
| 374 | { |
| 375 | if (phydev->drv->config) |
| 376 | phydev->drv->config(phydev); |
| 377 | |
| 378 | return 0; |
| 379 | } |
| 380 | |
| 381 | int board_early_init_f(void) |
| 382 | { |
| 383 | clock_init(); |
| 384 | mscm_init(); |
| 385 | |
| 386 | setup_iomux_uart(); |
| 387 | setup_iomux_enet(); |
Alison Wang | 86bef20 | 2013-06-17 15:30:38 +0800 | [diff] [blame] | 388 | setup_iomux_i2c(); |
Alison Wang | 695c9b5 | 2013-05-27 22:55:47 +0000 | [diff] [blame] | 389 | |
| 390 | return 0; |
| 391 | } |
| 392 | |
| 393 | int board_init(void) |
| 394 | { |
| 395 | /* address of boot parameters */ |
| 396 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 397 | |
| 398 | return 0; |
| 399 | } |
| 400 | |
| 401 | int checkboard(void) |
| 402 | { |
| 403 | puts("Board: vf610twr\n"); |
| 404 | |
| 405 | return 0; |
| 406 | } |