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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +01002/*
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +01003 * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +01004 */
Konrad Dybcio6c0b8442023-11-07 12:41:01 +00005#ifndef _CLOCK_QCOM_H
6#define _CLOCK_QCOM_H
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +01007
Caleb Connolly7a632942023-11-07 12:41:02 +00008#include <asm/io.h>
9
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +010010#define CFG_CLK_SRC_CXO (0 << 8)
11#define CFG_CLK_SRC_GPLL0 (1 << 8)
Dzmitry Sankouski038f2b92021-10-17 13:44:30 +030012#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +010013#define CFG_CLK_SRC_MASK (7 << 8)
14
Ramon Friedae299772018-05-16 12:13:39 +030015struct pll_vote_clk {
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +010016 uintptr_t status;
17 int status_bit;
18 uintptr_t ena_vote;
19 int vote_bit;
20};
21
Ramon Friedae299772018-05-16 12:13:39 +030022struct vote_clk {
23 uintptr_t cbcr_reg;
24 uintptr_t ena_vote;
25 int vote_bit;
26};
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +010027struct bcr_regs {
28 uintptr_t cfg_rcgr;
29 uintptr_t cmd_rcgr;
30 uintptr_t M;
31 uintptr_t N;
32 uintptr_t D;
33};
34
Caleb Connolly397c84f2023-11-07 12:41:05 +000035struct freq_tbl {
36 uint freq;
37 uint src;
38 u8 pre_div;
39 u16 m;
40 u16 n;
41};
42
43#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
44
Caleb Connolly7a632942023-11-07 12:41:02 +000045struct gate_clk {
46 uintptr_t reg;
47 u32 en_val;
48 const char *name;
49};
50
51#ifdef DEBUG
52#define GATE_CLK(clk, reg, val) [clk] = { reg, val, #clk }
53#else
54#define GATE_CLK(clk, reg, val) [clk] = { reg, val, NULL }
55#endif
56
Konrad Dybcio6c0b8442023-11-07 12:41:01 +000057struct qcom_reset_map {
58 unsigned int reg;
59 u8 bit;
60};
61
Volodymyr Babchukaae46492024-03-11 21:33:45 +000062struct qcom_power_map {
63 unsigned int reg;
64};
65
Caleb Connolly10a0abb2023-11-07 12:41:03 +000066struct clk;
67
Konrad Dybcio6c0b8442023-11-07 12:41:01 +000068struct msm_clk_data {
Volodymyr Babchukaae46492024-03-11 21:33:45 +000069 const struct qcom_power_map *power_domains;
70 unsigned long num_power_domains;
Konrad Dybcio6c0b8442023-11-07 12:41:01 +000071 const struct qcom_reset_map *resets;
72 unsigned long num_resets;
Caleb Connolly7a632942023-11-07 12:41:02 +000073 const struct gate_clk *clks;
74 unsigned long num_clks;
Caleb Connolly10a0abb2023-11-07 12:41:03 +000075
76 int (*enable)(struct clk *clk);
77 unsigned long (*set_rate)(struct clk *clk, unsigned long rate);
Konrad Dybcio6c0b8442023-11-07 12:41:01 +000078};
79
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +010080struct msm_clk_priv {
Konrad Dybcio6c0b8442023-11-07 12:41:01 +000081 phys_addr_t base;
82 struct msm_clk_data *data;
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +010083};
84
Konrad Dybcio6c0b8442023-11-07 12:41:01 +000085int qcom_cc_bind(struct udevice *parent);
Ramon Friedae299772018-05-16 12:13:39 +030086void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +010087void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
88void clk_enable_cbc(phys_addr_t cbcr);
Ramon Friedae299772018-05-16 12:13:39 +030089void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
Caleb Connolly397c84f2023-11-07 12:41:05 +000090const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate);
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +010091void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
Caleb Connollyfbacc672023-11-07 12:41:04 +000092 int div, int m, int n, int source, u8 mnd_width);
Sumit Garga3e804d2023-02-01 19:28:57 +053093void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
94 int source);
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +010095
Caleb Connolly7a632942023-11-07 12:41:02 +000096static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
97{
98 u32 val;
99 if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0)
100 return;
101
102 val = readl(priv->base + priv->data->clks[id].reg);
103 writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
104}
105
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +0100106#endif