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git01.mediatek.com / filogic / uboot / aad29aea5b775261af26bf17e400a193b18991df / . / arch / x86 / cpu / broadwell / adsp.c
blob: 1fa18237809cdfe9d1f9283a8701949bd94ce15c [file] [log] [blame]
Simon Glass398336e2019-02-16 20:25:01 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Support for Intel Application Digital Signal Processor
4 *
5 * Copyright 2019 Google LLC
6 *
7 * Modified from coreboot file of the same name
8 */
9
10#define LOG_CATEGORY UCLASS_SYSCON
11
12#include <common.h>
13#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]14#include <log.h>
Simon Glass398336e2019-02-16 20:25:01 -0700[diff] [blame]15#include <pci.h>
16#include <asm/io.h>
17#include <asm/cpu.h>
18#include <asm/intel_regs.h>
19#include <asm/arch/adsp.h>
20#include <asm/arch/pch.h>
21#include <asm/arch/rcb.h>
22
23enum pci_type_t {
24 LYNX_POINT,
25 WILDCAT_POINT,
26};
27
28struct broadwell_adsp_priv {
29 bool adsp_d3_pg_enable;
30 bool adsp_sram_pg_enable;
31 bool sio_acpi_mode;
32};
33
34static int broadwell_adsp_probe(struct udevice *dev)
35{
36 struct broadwell_adsp_priv *priv = dev_get_priv(dev);
37 enum pci_type_t type;
38 u32 bar0, bar1;
39 u32 tmp32;
40
41 /* Find BAR0 and BAR1 */
42 bar0 = dm_pci_read_bar32(dev, 0);
43 if (!bar0)
44 return -EINVAL;
45 bar1 = dm_pci_read_bar32(dev, 1);
46 if (!bar1)
47 return -EINVAL;
48
49 /*
50 * Set LTR value in DSP shim LTR control register to 3ms
51 * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h
52 */
53 type = dev_get_driver_data(dev);
54 tmp32 = type == WILDCAT_POINT ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT;
55 writel(ADSP_SHIM_LTRC_VALUE, bar0 + tmp32);
56
57 /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */
58 dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE);
59
60 /* Program ADSP IOBP VDLDAT1 to 0x040100 */
61 pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE);
62
63 /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
64 dm_pci_read_config32(dev, ADSP_PCI_VDRTCTL0, &tmp32);
65 if (type == WILDCAT_POINT) {
66 if (priv->adsp_d3_pg_enable) {
67 tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
68 if (priv->adsp_sram_pg_enable)
69 tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
70 else
71 tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
72 } else {
73 tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
74 }
75 } else {
76 if (priv->adsp_d3_pg_enable) {
77 tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
78 if (priv->adsp_sram_pg_enable)
79 tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
80 else
81 tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
82 } else {
83 tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
84 }
85 }
86 dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);
87
88 /* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */
89 setbits_le32(RCB_REG(0x3350), 1 << 10);
90
91 /* Set DSP IOBP PMCTL 0x1e0=0x3f */
92 pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE);
93
94 if (priv->sio_acpi_mode) {
95 /* Configure for ACPI mode */
96 log_info("ADSP: Enable ACPI Mode IRQ3\n");
97
98 /* Set interrupt de-assert/assert opcode override to IRQ3 */
99 pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3);
100
101 /* Enable IRQ3 in RCBA */
102 setbits_le32(RCB_REG(ACPIIRQEN), ADSP_ACPI_IRQEN);
103
104 /* Set ACPI Interrupt Enable Bit */
105 pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD,
106 ADSP_PCICFGCTL_ACPIIE);
107
108 /* Put ADSP in D3hot */
109 clrbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT);
110 } else {
111 log_info("ADSP: Enable PCI Mode IRQ23\n");
112
113 /* Configure for PCI mode */
114 dm_pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
115
116 /* Clear ACPI Interrupt Enable Bit */
117 pch_iobp_update(ADSP_IOBP_PCICFGCTL,
118 ~(ADSP_PCICFGCTL_SPCBAD |
119 ADSP_PCICFGCTL_ACPIIE), 0);
120 }
121
122 return 0;
123}
124
Simon Glassaad29ae2020-12-03 16:55:21 -0700[diff] [blame^]125static int broadwell_adsp_of_to_plat(struct udevice *dev)
Simon Glass398336e2019-02-16 20:25:01 -0700[diff] [blame]126{
127 struct broadwell_adsp_priv *priv = dev_get_priv(dev);
128
129 priv->adsp_d3_pg_enable = dev_read_bool(dev, "intel,adsp-d3-pg-enable");
130 priv->adsp_sram_pg_enable = dev_read_bool(dev,
131 "intel,adsp-sram-pg-enable");
132 priv->sio_acpi_mode = dev_read_bool(dev, "intel,sio-acpi-mode");
133
134 return 0;
135}
136
137static const struct udevice_id broadwell_adsp_ids[] = {
138 { .compatible = "intel,wildcatpoint-adsp", .data = WILDCAT_POINT },
139 { }
140};
141
142U_BOOT_DRIVER(broadwell_adsp_drv) = {
143 .name = "adsp",
144 .id = UCLASS_SYSCON,
Simon Glassaad29ae2020-12-03 16:55:21 -0700[diff] [blame^]145 .of_to_plat = broadwell_adsp_of_to_plat,
Simon Glass398336e2019-02-16 20:25:01 -0700[diff] [blame]146 .of_match = broadwell_adsp_ids,
147 .bind = dm_scan_fdt_dev,
148 .probe = broadwell_adsp_probe,
149};
150
151static struct pci_device_id broadwell_adsp_supported[] = {
152 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
153 PCI_DEVICE_ID_INTEL_WILDCATPOINT_ADSP) },
154 { },
155};
156
157U_BOOT_PCI_DEVICE(broadwell_adsp_drv, broadwell_adsp_supported);