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git01.mediatek.com / filogic / uboot / aaa2a1914cefd0a633609eb3d7e3a52a11ec73e8 / . / cpu / mcf52x2 / start.S
blob: 8a83ca5ef7dd933b0ec0e8185892eabb86fcd558 [file] [log] [blame]
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include "version.h"
26
27#ifndef CONFIG_IDENT_STRING
28#define CONFIG_IDENT_STRING ""
29#endif
30
31
32#define _START _start
33#define _FAULT _fault
34
35
36#define SAVE_ALL \
37 move.w #0x2700,%sr; /* disable intrs */ \
38 subl #60,%sp; /* space for 15 regs */ \
39 moveml %d0-%d7/%a0-%a6,%sp@; \
40
41#define RESTORE_ALL \
42 moveml %sp@,%d0-%d7/%a0-%a6; \
43 addl #60,%sp; /* space for 15 regs */ \
44 rte
45
46/* If we come from a pre-loader we don't need an initial exception
47 * table.
48 */
49#if !defined(CONFIG_MONITOR_IS_IN_RAM)
50
51.text
52/*
53 * Vector table. This is used for initial platform startup.
54 * These vectors are to catch any un-intended traps.
55 */
56_vectors:
57
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200[diff] [blame]58.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
59#if defined(CONFIG_R5200)
60.long 0x400
61#elif defined(CONFIG_M5282)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]62.long _start - TEXT_BASE
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]63#else
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200[diff] [blame]64.long _START
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]65#endif
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200[diff] [blame]66
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102
103#endif
104
105 .text
106
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]107
108#if defined(CFG_INT_FLASH_BASE) && \
109 (defined(CONFIG_M5282) || defined(CONFIG_M5281))
110 #if (TEXT_BASE == CFG_INT_FLASH_BASE)
111 .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
112 .long 0xFFFFFFFF /* all sectors protected */
113 .long 0x00000000 /* supervisor/User restriction */
114 .long 0x00000000 /* programm/data space restriction */
115 .long 0x00000000 /* Flash security */
116 #endif
117#endif
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]118 .globl _start
119_start:
120 nop
121 nop
122 move.w #0x2700,%sr
123
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]124#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]125 move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
126 move.c %d0, %MBAR
127
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]128 /*** The 5249 has MBAR2 as well ***/
129#ifdef CFG_MBAR2
130 move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */
131 movec %d0, #0xc0e /* Set MBAR2 */
132#endif
133
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]134 move.l #(CFG_INIT_RAM_ADDR + 1), %d0
135 movec %d0, %RAMBAR0
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]136#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]137
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200[diff] [blame]138#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]139 /* Initialize IPSBAR */
140 move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
141 move.l %d0, 0x40000000
142
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]143 /* Initialize RAMBAR1: locate SRAM and validate it */
144 move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
145 movec %d0, %RAMBAR1
146
147#if (TEXT_BASE == CFG_INT_FLASH_BASE)
148 /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
149
150 move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
151 move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
152 move.l #(CFG_INIT_RAM_ADDR), %a2
153_copy_flash:
154 move.l (%a0)+, (%a2)+
155 cmp.l %a0, %a1
156 bgt.s _copy_flash
157 jmp CFG_INIT_RAM_ADDR
158
159_flashbar_setup:
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]160 /* Initialize FLASHBAR: locate internal Flash and validate it */
161 move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
162 movec %d0, %RAMBAR0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]163 jmp _after_flashbar_copy.L /* Force jump to absolute address */
164_flashbar_setup_end:
165 nop
166_after_flashbar_copy:
167#else
168 /* Setup code to initialize FLASHBAR, if start from external Memory */
169 move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
170 movec %d0, %RAMBAR0
171#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]172
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]173#endif
174 /* if we come from a pre-loader we have no exception table and
175 * therefore no VBR to set
176 */
177#if !defined(CONFIG_MONITOR_IS_IN_RAM)
178 move.l #CFG_FLASH_BASE, %d0
179 movec %d0, %VBR
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]180#endif
181
182#ifdef CONFIG_R5200
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]183 move.l #(_flash_setup-CFG_FLASH_BASE), %a0
184 move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1
185 move.l #(CFG_INIT_RAM_ADDR), %a2
186_copy_flash:
187 move.l (%a0)+, (%a2)+
188 cmp.l %a0, %a1
189 bgt.s _copy_flash
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]190 jmp CFG_INIT_RAM_ADDR
191_after_flash_copy:
192#endif
193
194#if 0
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]195 /* invalidate and disable cache */
196 move.l #0x01000000, %d0 /* Invalidate cache cmd */
197 movec %d0, %CACR /* Invalidate cache */
198 move.l #0, %d0
199 movec %d0, %ACR0
200 movec %d0, %ACR1
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]201#endif
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]202
203 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */
204 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
205 clr.l %sp@-
206
207 move.l #__got_start, %a5 /* put relocation table address to a5 */
208
209 bsr cpu_init_f /* run low-level CPU init code (from flash) */
210 bsr board_init_f /* run low-level board init code (from flash) */
211
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]212 /* board_init_f() does not return */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]213
214/*------------------------------------------------------------------------------*/
215
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]216#ifdef CONFIG_R5200
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]217_flash_setup:
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]218 /* CSAR0 */
219 move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]220 move.w %d0, 0x40000080
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]221
222 /* CSCR0 */
223 move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]224 move.w %d0, 0x4000008A
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]225
226 /* CSMR0 */
227 move.l #0x001f0001, %d0 /* 2 MB, valid */
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]228 move.l %d0, 0x40000084
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]229
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]230 jmp _after_flash_copy.L
231_flash_setup_end:
232#endif
233
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]234/*
235 * void relocate_code (addr_sp, gd, addr_moni)
236 *
237 * This "function" does not return, instead it continues in RAM
238 * after relocating the monitor code.
239 *
240 * r3 = dest
241 * r4 = src
242 * r5 = length in bytes
243 * r6 = cachelinesize
244 */
245 .globl relocate_code
246relocate_code:
247 link.w %a6,#0
248 move.l 8(%a6), %sp /* set new stack pointer */
249
250 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
251 move.l 16(%a6), %a0 /* Save copy of Destination Address */
252
253 move.l #CFG_MONITOR_BASE, %a1
254 move.l #__init_end, %a2
255 move.l %a0, %a3
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]256 /* copy the code to RAM */
2571:
258 move.l (%a1)+, (%a3)+
259 cmp.l %a1,%a2
260 bgt.s 1b
261
262/*
263 * We are done. Do not return, instead branch to second part of board
264 * initialization, now running from RAM.
265 */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]266 move.l %a0, %a1
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]267 add.l #(in_ram - CFG_MONITOR_BASE), %a1
268 jmp (%a1)
269
270in_ram:
271
272clear_bss:
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]273 /*
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]274 * Now clear BSS segment
275 */
276 move.l %a0, %a1
277 add.l #(_sbss - CFG_MONITOR_BASE),%a1
278 move.l %a0, %d1
279 add.l #(_ebss - CFG_MONITOR_BASE),%d1
2806:
281 clr.l (%a1)+
282 cmp.l %a1,%d1
283 bgt.s 6b
284
285 /*
286 * fix got table in RAM
287 */
288 move.l %a0, %a1
289 add.l #(__got_start - CFG_MONITOR_BASE),%a1
290 move.l %a1,%a5 /* * fix got pointer register a5 */
291
292 move.l %a0, %a2
293 add.l #(__got_end - CFG_MONITOR_BASE),%a2
294
2957:
296 move.l (%a1),%d1
297 sub.l #_start,%d1
298 add.l %a0,%d1
299 move.l %d1,(%a1)+
300 cmp.l %a2, %a1
301 bne 7b
302
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]303#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
304 /* patch the 3 accesspoints to 3 ichache_state */
305 /* quick and dirty */
306
307 move.l %a0,%d1
308 add.l #(icache_state - CFG_MONITOR_BASE),%d1
309 move.l %a0,%a1
310 add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
311 move.l %d1,(%a1)
312 move.l %a0,%a1
313 add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
314 move.l %d1,(%a1)
315 move.l %a0,%a1
316 add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
317 move.l %d1,(%a1)
318#endif
319
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]320 /* calculate relative jump to board_init_r in ram */
321 move.l %a0, %a1
322 add.l #(board_init_r - CFG_MONITOR_BASE), %a1
323
324 /* set parameters for board_init_r */
325 move.l %a0,-(%sp) /* dest_addr */
326 move.l %d0,-(%sp) /* gd */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]327 #if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
328 defined(CFG_HALT_BEFOR_RAM_JUMP)
329 halt
330 #endif
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]331 jsr (%a1)
332
333/*------------------------------------------------------------------------------*/
334/* exception code */
335 .globl _fault
336_fault:
337 jmp _fault
338
339 .globl _exc_handler
340_exc_handler:
341 SAVE_ALL
342 movel %sp,%sp@-
343 bsr exc_handler
344 addql #4,%sp
345 RESTORE_ALL
346
347 .globl _int_handler
348_int_handler:
349 SAVE_ALL
350 movel %sp,%sp@-
351 bsr int_handler
352 addql #4,%sp
353 RESTORE_ALL
354
355/*------------------------------------------------------------------------------*/
356/* cache functions */
357#ifdef CONFIG_M5272
358 .globl icache_enable
359icache_enable:
360 move.l #0x01000000, %d0 /* Invalidate cache cmd */
361 movec %d0, %CACR /* Invalidate cache */
362 move.l #0x0000c000, %d0 /* Setup cache mask */
363 movec %d0, %ACR0 /* Enable cache */
364 move.l #0xff00c000, %d0 /* Setup cache mask */
365 movec %d0, %ACR1 /* Enable cache */
366 move.l #0x80000100, %d0 /* Setup cache mask */
367 movec %d0, %CACR /* Enable cache */
368 moveq #1, %d0
369 move.l %d0, icache_state
370 rts
371#endif
372
373#ifdef CONFIG_M5282
374 .globl icache_enable
375icache_enable:
376 move.l #0x01000000, %d0 /* Invalidate cache cmd */
377 movec %d0, %CACR /* Invalidate cache */
378 move.l #0x0000c000, %d0 /* Setup cache mask */
379 movec %d0, %ACR0 /* Enable cache */
380 move.l #0xff00c000, %d0 /* Setup cache mask */
381 movec %d0, %ACR1 /* Enable cache */
382 move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
383 movec %d0, %CACR /* Enable cache */
384 moveq #1, %d0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]385icache_state_access_1:
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]386 move.l %d0, icache_state
387 rts
388#endif
389
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]390#ifdef CONFIG_M5249
391 .globl icache_enable
392icache_enable:
393 /*
394 * Note: The 5249 Documentation doesn't give a bit position for CINV!
395 * From the 5272 and the 5307 documentation, I have deduced that it is
396 * probably CACR[24]. Should someone say something to Motorola?
397 * ~Jeremy
398 */
399 move.l #0x01000000, %d0 /* Invalidate whole cache */
400 move.c %d0,%CACR
401 move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */
402 move.c %d0, %ACR0
403 move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */
404 move.c %d0, %ACR1
405 move.l #0x90000200, %d0 /* Set cache enable cmd */
406 move.c %d0,%CACR
407 moveq #1, %d0
408 move.l %d0, icache_state
409 rts
410#endif
411
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]412 .globl icache_disable
413icache_disable:
414 move.l #0x00000100, %d0 /* Setup cache mask */
415 movec %d0, %CACR /* Enable cache */
416 clr.l %d0 /* Setup cache mask */
417 movec %d0, %ACR0 /* Enable cache */
418 movec %d0, %ACR1 /* Enable cache */
419 moveq #0, %d0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]420icache_state_access_2:
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]421 move.l %d0, icache_state
422 rts
423
424 .globl icache_status
425icache_status:
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]426icache_state_access_3:
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]427 move.l icache_state, %d0
428 rts
429
430 .data
431icache_state:
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]432 .long 0 /* cache is diabled on inirialization */
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]433
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]434/*------------------------------------------------------------------------------*/
435
436 .globl version_string
437version_string:
438 .ascii U_BOOT_VERSION
439 .ascii " (", __DATE__, " - ", __TIME__, ")"
440 .ascii CONFIG_IDENT_STRING, "\0"