blob: f7d71c3612a15293f3952eb18db6c0b23a09f481 [file] [log] [blame]
Bin Meng03b341b2015-04-27 23:22:24 +08001#
2# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3#
4# SPDX-License-Identifier: GPL-2.0+
5#
6
7if VENDOR_INTEL
8
9choice
10 prompt "Mainboard model"
Joe Hershbergerf0699602015-05-12 14:46:23 -050011 optional
Bin Meng03b341b2015-04-27 23:22:24 +080012
Bin Menge1c49352015-07-30 03:49:17 -070013config TARGET_BAYLEYBAY
14 bool "Bayley Bay"
15 help
16 This is the Intel Bayley Bay Customer Reference Board. It contains an
17 Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
18 4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
19 PCIe and some other sensor interfaces.
20
Bin Meng03b341b2015-04-27 23:22:24 +080021config TARGET_CROWNBAY
22 bool "Crown Bay"
23 help
24 This is the Intel Crown Bay Customer Reference Board. It contains
25 the Intel Atom Processor E6xx populated on the COM Express module
26 with 1GB DDR2 soldered down memory and a carrier board with the
27 Intel Platform Controller Hub EG20T, other system components and
28 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
29
30config TARGET_GALILEO
31 bool "Galileo"
32 help
33 This is the Intel Galileo board, which is the first in a family of
34 Arduino-certified development and prototyping boards based on Intel
35 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
36 single-core, single-thread, Intel Pentium processor instrunction set
37 architecture (ISA) compatible, operating at speeds up to 400Mhz,
38 along with 256MB DDR3 memory. It supports a wide range of industry
39 standard I/O interfaces, including a full-sized mini-PCIe slot,
40 one 100Mb Ethernet port, a microSD card slot, a USB host port and
41 a USB client port.
42
43config TARGET_MINNOWMAX
44 bool "Minnowboard MAX"
45 help
46 This is the Intel Minnowboard MAX. It contains an Atom E3800
47 processor in a small form factor with Ethernet, micro-SD, USB 2,
48 USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
49 It requires some binary blobs - see README.x86 for details.
50
51 Note that PCIE_ECAM_BASE is set up by the FSP so the value used
52 by U-Boot matches that value.
53
54endchoice
55
Bin Menge1c49352015-07-30 03:49:17 -070056source "board/intel/bayleybay/Kconfig"
Bin Meng03b341b2015-04-27 23:22:24 +080057source "board/intel/crownbay/Kconfig"
58source "board/intel/galileo/Kconfig"
59source "board/intel/minnowmax/Kconfig"
60
61endif