| Stephen Warren | 1ce3d54 | 2016-05-12 13:32:56 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2016, NVIDIA CORPORATION. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0 |
| 5 | */ |
| 6 | |
| 7 | #ifndef _P2771_0000_H |
| 8 | #define _P2771_0000_H |
| 9 | |
| 10 | #include <linux/sizes.h> |
| 11 | |
| 12 | #include "tegra186-common.h" |
| 13 | |
| 14 | /* High-level configuration options */ |
| 15 | #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" |
| 16 | |
| 17 | /* SD/MMC */ |
| 18 | #define CONFIG_MMC |
| 19 | #define CONFIG_GENERIC_MMC |
| 20 | #define CONFIG_TEGRA_MMC |
| 21 | |
| 22 | /* Environment in eMMC, at the end of 2nd "boot sector" */ |
| 23 | #define CONFIG_ENV_IS_IN_MMC |
| 24 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 25 | #define CONFIG_SYS_MMC_ENV_PART 2 |
| 26 | #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) |
| 27 | |
| 28 | #include "tegra-common-post.h" |
| 29 | |
| 30 | /* Crystal is 38.4MHz. clk_m runs at half that rate */ |
| 31 | #define COUNTER_FREQUENCY 19200000 |
| 32 | |
| 33 | #endif |