Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / aa6e0555069e778326f4ca56d4c9173bf5da5f3b / . / drivers / pinctrl / rockchip / pinctrl-rk3568.c
blob: 314edb5a60648e0e7069fdb5f397fcc42510b370 [file] [log] [blame]
Jagan Teki7fc80642023-02-17 17:28:43 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <dm/pinctrl.h>
9#include <regmap.h>
10#include <syscon.h>
11#include <dt-bindings/pinctrl/rockchip.h>
12
13#include "pinctrl-rockchip.h"
14
15static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
Jonas Karlman3a8a2992023-04-17 19:07:23 +0000[diff] [blame]16 MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */
17 MR_PMUGRF(RK_GPIO0, RK_PC7, RK_FUNC_2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */
18 MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */
19 MR_PMUGRF(RK_GPIO0, RK_PB5, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */
20 MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */
21 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */
Jagan Teki7fc80642023-02-17 17:28:43 +0530[diff] [blame]22 MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */
23 MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */
24 MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */
25 MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */
26 MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */
27 MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */
28 MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */
29 MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */
30 MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */
31 MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */
32 MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */
33 MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */
34 MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */
35 MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */
36 MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */
37 MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */
38 MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */
39 MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */
40 MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */
41 MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */
Jonas Karlman3a8a2992023-04-17 19:07:23 +0000[diff] [blame]42 MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */
43 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */
44 MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */
45 MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */
46 MR_TOPGRF(RK_GPIO3, RK_PB5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */
47 MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */
48 MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */
49 MR_TOPGRF(RK_GPIO4, RK_PC0, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */
50 MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */
51 MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */
52 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */
53 MR_TOPGRF(RK_GPIO4, RK_PC6, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */
54 MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */
55 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */
56 MR_TOPGRF(RK_GPIO3, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */
57 MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */
Jagan Teki7fc80642023-02-17 17:28:43 +0530[diff] [blame]58 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */
59 MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */
60 MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */
61 MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */
62 MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */
63 MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */
64 MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */
65 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */
66 MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */
67 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */
68 MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */
Jonas Karlman3a8a2992023-04-17 19:07:23 +0000[diff] [blame]69 MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */
Jagan Teki7fc80642023-02-17 17:28:43 +0530[diff] [blame]70 MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */
71 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */
72 MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */
73 MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */
74 MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */
75 MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */
76 MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */
77 MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */
78 MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */
79 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */
80 MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */
81 MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */
Jonas Karlman3a8a2992023-04-17 19:07:23 +0000[diff] [blame]82 MR_TOPGRF(RK_GPIO4, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */
Jagan Teki7fc80642023-02-17 17:28:43 +0530[diff] [blame]83 MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */
84 MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */
85 MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */
86 MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */
87 MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */
88 MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */
89 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */
90 MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */
91 MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */
92 MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */
93 MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */
94 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */
Jonas Karlman3a8a2992023-04-17 19:07:23 +0000[diff] [blame]95 MR_TOPGRF(RK_GPIO1, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */
96 MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */
97 MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */
98 MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */
99 MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */
Jagan Teki7fc80642023-02-17 17:28:43 +0530[diff] [blame]100 MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */
101 MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */
102 MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */
103 MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */
104 MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */
105 MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */
106 MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */
107 MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */
108 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */
109};
110
111static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
112{
113 struct rockchip_pinctrl_priv *priv = bank->priv;
114 int iomux_num = (pin / 8);
115 struct regmap *regmap;
116 int reg, ret, mask;
117 u8 bit;
118 u32 data;
119
120 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
121
122 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
123 regmap = priv->regmap_pmu;
124 else
125 regmap = priv->regmap_base;
126
127 reg = bank->iomux[iomux_num].offset;
128 if ((pin % 8) >= 4)
129 reg += 0x4;
130 bit = (pin % 4) * 4;
131 mask = 0xf;
132
133 data = (mask << (bit + 16));
134 data |= (mux & mask) << bit;
135 ret = regmap_write(regmap, reg, data);
136
137 return ret;
138}
139
140#define RK3568_PULL_PMU_OFFSET 0x20
141#define RK3568_PULL_GRF_OFFSET 0x80
142#define RK3568_PULL_BITS_PER_PIN 2
143#define RK3568_PULL_PINS_PER_REG 8
144#define RK3568_PULL_BANK_STRIDE 0x10
145
146static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
147 int pin_num, struct regmap **regmap,
148 int *reg, u8 *bit)
149{
150 struct rockchip_pinctrl_priv *info = bank->priv;
151
152 if (bank->bank_num == 0) {
153 *regmap = info->regmap_pmu;
154 *reg = RK3568_PULL_PMU_OFFSET;
155 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
156 } else {
157 *regmap = info->regmap_base;
158 *reg = RK3568_PULL_GRF_OFFSET;
159 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
160 }
161
162 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
163 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
164 *bit *= RK3568_PULL_BITS_PER_PIN;
165}
166
167#define RK3568_DRV_PMU_OFFSET 0x70
168#define RK3568_DRV_GRF_OFFSET 0x200
169#define RK3568_DRV_BITS_PER_PIN 8
170#define RK3568_DRV_PINS_PER_REG 2
171#define RK3568_DRV_BANK_STRIDE 0x40
172
173static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
174 int pin_num, struct regmap **regmap,
175 int *reg, u8 *bit)
176{
177 struct rockchip_pinctrl_priv *info = bank->priv;
178
179 /* The first 32 pins of the first bank are located in PMU */
180 if (bank->bank_num == 0) {
181 *regmap = info->regmap_pmu;
182 *reg = RK3568_DRV_PMU_OFFSET;
183 } else {
184 *regmap = info->regmap_base;
185 *reg = RK3568_DRV_GRF_OFFSET;
186 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
187 }
188
189 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
190 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
191 *bit *= RK3568_DRV_BITS_PER_PIN;
192}
193
194#define RK3568_SCHMITT_BITS_PER_PIN 2
195#define RK3568_SCHMITT_PINS_PER_REG 8
196#define RK3568_SCHMITT_BANK_STRIDE 0x10
197#define RK3568_SCHMITT_GRF_OFFSET 0xc0
198#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
199
200static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
201 int pin_num, struct regmap **regmap,
202 int *reg, u8 *bit)
203{
204 struct rockchip_pinctrl_priv *info = bank->priv;
205
206 if (bank->bank_num == 0) {
207 *regmap = info->regmap_pmu;
208 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
209 } else {
210 *regmap = info->regmap_base;
211 *reg = RK3568_SCHMITT_GRF_OFFSET;
212 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
213 }
214
215 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
216 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
217 *bit *= RK3568_SCHMITT_BITS_PER_PIN;
218
219 return 0;
220}
221
222static int rk3568_set_pull(struct rockchip_pin_bank *bank,
223 int pin_num, int pull)
224{
225 struct regmap *regmap;
226 int reg, ret;
227 u8 bit, type;
228 u32 data;
229
230 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
231 return -ENOTSUPP;
232
233 rk3568_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
234 type = bank->pull_type[pin_num / 8];
235 ret = rockchip_translate_pull_value(type, pull);
236 if (ret < 0) {
237 debug("unsupported pull setting %d\n", pull);
238 return ret;
239 }
240
Jonas Karlman3a8a2992023-04-17 19:07:23 +0000[diff] [blame]241 /*
242 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
243 * where that pull up value becomes 3.
244 */
245 if (bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
246 if (ret == 1)
247 ret = 3;
248 }
249
Jagan Teki7fc80642023-02-17 17:28:43 +0530[diff] [blame]250 /* enable the write to the equivalent lower bits */
251 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
252
253 data |= (ret << bit);
254 ret = regmap_write(regmap, reg, data);
255
256 return ret;
257}
258
259static int rk3568_set_drive(struct rockchip_pin_bank *bank,
260 int pin_num, int strength)
261{
262 struct regmap *regmap;
263 int reg;
264 u32 data;
265 u8 bit;
266 int drv = (1 << (strength + 1)) - 1;
267 int ret = 0;
268
269 rk3568_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
270
271 /* enable the write to the equivalent lower bits */
272 data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
273 data |= (drv << bit);
274
275 ret = regmap_write(regmap, reg, data);
276 if (ret)
277 return ret;
278
279 if (bank->bank_num == 1 && pin_num == 21)
280 reg = 0x0840;
281 else if (bank->bank_num == 2 && pin_num == 2)
282 reg = 0x0844;
283 else if (bank->bank_num == 2 && pin_num == 8)
284 reg = 0x0848;
285 else if (bank->bank_num == 3 && pin_num == 0)
286 reg = 0x084c;
287 else if (bank->bank_num == 3 && pin_num == 6)
288 reg = 0x0850;
289 else if (bank->bank_num == 4 && pin_num == 0)
290 reg = 0x0854;
291 else
292 return 0;
293
294 data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
295 data |= drv;
296
297 return regmap_write(regmap, reg, data);
298}
299
300static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
301 int pin_num, int enable)
302{
303 struct regmap *regmap;
304 int reg;
305 u32 data;
306 u8 bit;
307
308 rk3568_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
309
310 /* enable the write to the equivalent lower bits */
311 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
312 data |= (enable << bit);
313
314 return regmap_write(regmap, reg, data);
315}
316
317static struct rockchip_pin_bank rk3568_pin_banks[] = {
318 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
319 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
320 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
321 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
322 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
323 IOMUX_WIDTH_4BIT,
324 IOMUX_WIDTH_4BIT,
325 IOMUX_WIDTH_4BIT),
326 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
327 IOMUX_WIDTH_4BIT,
328 IOMUX_WIDTH_4BIT,
329 IOMUX_WIDTH_4BIT),
330 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
331 IOMUX_WIDTH_4BIT,
332 IOMUX_WIDTH_4BIT,
333 IOMUX_WIDTH_4BIT),
334 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
335 IOMUX_WIDTH_4BIT,
336 IOMUX_WIDTH_4BIT,
337 IOMUX_WIDTH_4BIT),
338};
339
340static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
341 .pin_banks = rk3568_pin_banks,
342 .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
343 .nr_pins = 160,
344 .grf_mux_offset = 0x0,
345 .pmu_mux_offset = 0x0,
346 .iomux_routes = rk3568_mux_route_data,
347 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
348 .set_mux = rk3568_set_mux,
349 .set_pull = rk3568_set_pull,
350 .set_drive = rk3568_set_drive,
351 .set_schmitt = rk3568_set_schmitt,
352};
353
354static const struct udevice_id rk3568_pinctrl_ids[] = {
355 {
356 .compatible = "rockchip,rk3568-pinctrl",
357 .data = (ulong)&rk3568_pin_ctrl
358 },
359 { }
360};
361
362U_BOOT_DRIVER(pinctrl_rk3568) = {
363 .name = "rockchip_rk3568_pinctrl",
364 .id = UCLASS_PINCTRL,
365 .of_match = rk3568_pinctrl_ids,
366 .priv_auto = sizeof(struct rockchip_pinctrl_priv),
367 .ops = &rockchip_pinctrl_ops,
368#if CONFIG_IS_ENABLED(OF_REAL)
369 .bind = dm_scan_fdt_dev,
370#endif
371 .probe = rockchip_pinctrl_probe,
372};