| Peter Robinson | 0b437a0 | 2022-12-31 09:24:00 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2016 Rockchip Electronics Co., Ltd |
| 4 | * (C) Copyright 2022 Peter Robinson <pbrobinson at gmail.com> |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <dm.h> |
| 9 | #include <init.h> |
| 10 | #include <syscon.h> |
| 11 | #include <asm/io.h> |
| 12 | #include <asm/arch-rockchip/clock.h> |
| 13 | #include <asm/arch-rockchip/grf_rk3399.h> |
| 14 | #include <asm/arch-rockchip/hardware.h> |
| 15 | #include <asm/arch-rockchip/misc.h> |
| 16 | #include <power/regulator.h> |
| 17 | |
| Ondrej Jirman | 2a1b628 | 2023-05-25 15:27:08 +0200 | [diff] [blame] | 18 | #define GRF_IO_VSEL_BT565_GPIO2AB 1 |
| 19 | #define GRF_IO_VSEL_AUDIO_GPIO3D4A 2 |
| Peter Robinson | 0b437a0 | 2022-12-31 09:24:00 +0000 | [diff] [blame] | 20 | #define PMUGRF_CON0_VSEL_SHIFT 8 |
| 21 | |
| 22 | #ifndef CONFIG_SPL_BUILD |
| 23 | int board_early_init_f(void) |
| 24 | { |
| 25 | struct udevice *regulator; |
| 26 | int ret; |
| 27 | |
| 28 | ret = regulator_get_by_platname("vcc5v0_usb", ®ulator); |
| 29 | if (ret) { |
| 30 | pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret); |
| 31 | goto out; |
| 32 | } |
| 33 | |
| 34 | ret = regulator_set_enable(regulator, true); |
| 35 | if (ret) |
| 36 | pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret); |
| 37 | |
| 38 | out: |
| 39 | return 0; |
| 40 | } |
| 41 | #endif |
| 42 | |
| 43 | #ifdef CONFIG_MISC_INIT_R |
| 44 | static void setup_iodomain(void) |
| 45 | { |
| 46 | struct rk3399_grf_regs *grf = |
| 47 | syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
| 48 | struct rk3399_pmugrf_regs *pmugrf = |
| 49 | syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); |
| 50 | |
| 51 | /* BT565 is in 1.8v domain */ |
| Ondrej Jirman | 2a1b628 | 2023-05-25 15:27:08 +0200 | [diff] [blame] | 52 | rk_setreg(&grf->io_vsel, |
| 53 | GRF_IO_VSEL_BT565_GPIO2AB | GRF_IO_VSEL_AUDIO_GPIO3D4A); |
| Peter Robinson | 0b437a0 | 2022-12-31 09:24:00 +0000 | [diff] [blame] | 54 | |
| 55 | /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ |
| 56 | rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); |
| 57 | } |
| 58 | |
| 59 | int misc_init_r(void) |
| 60 | { |
| 61 | const u32 cpuid_offset = 0x7; |
| 62 | const u32 cpuid_length = 0x10; |
| 63 | u8 cpuid[cpuid_length]; |
| 64 | int ret; |
| 65 | |
| 66 | setup_iodomain(); |
| 67 | |
| 68 | ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); |
| 69 | if (ret) |
| 70 | return ret; |
| 71 | |
| 72 | ret = rockchip_cpuid_set(cpuid, cpuid_length); |
| 73 | if (ret) |
| 74 | return ret; |
| 75 | |
| 76 | return ret; |
| 77 | } |
| 78 | #endif |