| Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 1 | Overview |
| 2 | -------- |
| 3 | P1_P2_RDB_PC represents a set of boards including |
| 4 | P1020MSBG-PC |
| 5 | P1020RDB-PC |
| Haijun.Zhang | a434d0a | 2013-06-28 10:47:09 +0800 | [diff] [blame] | 6 | P1020RDB-PD |
| Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 7 | P1021RDB-PC |
| 8 | P1024RDB |
| Li Yang | 5f99973 | 2011-07-26 09:50:46 -0500 | [diff] [blame] | 9 | P2020RDB-PC |
| 10 | |
| 11 | They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC |
| 12 | has 64-bit DDR. All others have 32-bit DDR. |
| 13 | |
| 14 | Key features on these boards include: |
| 15 | * DDR3 |
| 16 | * NOR flash |
| 17 | * NAND flash (on RDB's only) |
| 18 | * SPI flash (on RDB's only) |
| 19 | * SDHC/MMC card slot |
| 20 | * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) |
| 21 | * PCIE slot and mini-PCIE slots |
| 22 | |
| 23 | As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM |
| 24 | is used to store SPD data. In case of absent or corrupted SPD, falling back |
| 25 | to timing data embedded in the source code will be used. Raw timing data is |
| 26 | extracted from DDR chip datasheet. Different speeds of DDR are supported with |
| 27 | this approach. ODT option is forced to fit this set of boards, again because |
| 28 | they don't have regular DIMMs. |
| 29 | |
| 30 | CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification |
| 31 | for writing timing. |
| 32 | |
| 33 | VSC firmware Address is defined by default in config file for eTSEC1. |
| 34 | |
| 35 | SD width is based off DIP switch. DIP switch is detected on the |
| 36 | board by reading i2c bus and setting the appropriate mux values. |
| 37 | |
| 38 | Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have |
| 39 | pins multiplexing. QE function needs to be disabled to access Nor Flash and |
| 40 | CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" |
| 41 | in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to |
| 42 | enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below |
| 43 | |
| 44 | 'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. |
| 45 | 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. |
| Hou Zhiqiang | 224999f | 2019-08-20 09:35:28 +0000 | [diff] [blame] | 46 | |
| 47 | Device tree support and how to enable it for different configs |
| 48 | -------------------------------------------------------------- |
| Hou Zhiqiang | 1a2961d | 2019-08-20 09:35:29 +0000 | [diff] [blame] | 49 | Device tree support is available for p1020rdb and p2020rdb for below mentioned boot, |
| Hou Zhiqiang | 224999f | 2019-08-20 09:35:28 +0000 | [diff] [blame] | 50 | 1. NOR Boot |
| 51 | 2. NAND Boot |
| 52 | 3. SD Boot |
| 53 | 4. SPIFLASH Boot |
| 54 | |
| 55 | To enable device tree support for other boot, below configs need to be |
| 56 | enabled in relative defconfig file, |
| 57 | 1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required) |
| 58 | 2. CONFIG_OF_CONTROL |
| 59 | 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at |
| Tom Rini | aac8149 | 2022-12-04 10:13:40 -0500 | [diff] [blame] | 60 | CFG_RESET_VECTOR_ADDRESS - 0xffc |
| Hou Zhiqiang | 224999f | 2019-08-20 09:35:28 +0000 | [diff] [blame] | 61 | |
| 62 | If device tree support is enabled in defconfig, |
| Pali Rohár | c685084 | 2022-08-01 17:42:20 +0200 | [diff] [blame] | 63 | 1. use 'u-boot.bin' for NOR boot. |
| Hou Zhiqiang | 224999f | 2019-08-20 09:35:28 +0000 | [diff] [blame] | 64 | 2. use 'u-boot-with-spl.bin' for other boot. |