Masahiro Yamada | d5f8fee | 2015-03-12 13:24:39 +0900 | [diff] [blame] | 1 | CONFIG_PPC=y |
Tom Rini | 07edfae | 2018-02-03 12:10:38 -0500 | [diff] [blame] | 2 | CONFIG_SYS_TEXT_BASE=0x00100000 |
Simon Glass | e076d6f | 2016-09-12 23:18:56 -0600 | [diff] [blame] | 3 | CONFIG_SPL_SERIAL_SUPPORT=y |
Tom Rini | 9bd0962 | 2018-04-07 20:27:54 -0400 | [diff] [blame] | 4 | CONFIG_SPL=y |
Mario Six | d10f318 | 2019-01-21 09:17:53 +0100 | [diff] [blame] | 5 | CONFIG_SYS_CLK_FREQ=66666667 |
Masahiro Yamada | d5f8fee | 2015-03-12 13:24:39 +0900 | [diff] [blame] | 6 | CONFIG_MPC83xx=y |
Mario Six | 4a50e56 | 2019-01-21 09:17:56 +0100 | [diff] [blame] | 7 | CONFIG_HIGH_BATS=y |
Mario Six | 7299dec | 2019-01-21 09:17:36 +0100 | [diff] [blame] | 8 | CONFIG_TARGET_MPC8313ERDB_NAND=y |
Mario Six | 9486710 | 2019-01-21 09:17:54 +0100 | [diff] [blame] | 9 | CONFIG_CORE_PLL_RATIO_2_1=y |
| 10 | CONFIG_PCI_HOST_MODE_ENABLE=y |
| 11 | CONFIG_PCI_INT_ARBITER1_ENABLE=y |
| 12 | CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y |
| 13 | CONFIG_TSEC1_MODE_RGMII=y |
| 14 | CONFIG_TSEC2_MODE_RGMII=y |
Mario Six | a861ea6 | 2019-01-21 09:17:57 +0100 | [diff] [blame] | 15 | CONFIG_BAT0=y |
| 16 | CONFIG_BAT0_NAME="DDR" |
| 17 | CONFIG_BAT0_BASE=0x00000000 |
| 18 | CONFIG_BAT0_LENGTH_256_MBYTES=y |
| 19 | CONFIG_BAT0_ACCESS_RW=y |
| 20 | CONFIG_BAT0_USER_MODE_VALID=y |
| 21 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y |
| 22 | CONFIG_BAT1=y |
| 23 | CONFIG_BAT1_NAME="PCI1_MEM" |
| 24 | CONFIG_BAT1_BASE=0x80000000 |
| 25 | CONFIG_BAT1_LENGTH_256_MBYTES=y |
| 26 | CONFIG_BAT1_ACCESS_RW=y |
| 27 | CONFIG_BAT1_USER_MODE_VALID=y |
| 28 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y |
| 29 | CONFIG_BAT2=y |
| 30 | CONFIG_BAT2_NAME="PCI1_MMIO_BASE" |
| 31 | CONFIG_BAT2_BASE=0x90000000 |
| 32 | CONFIG_BAT2_LENGTH_256_MBYTES=y |
| 33 | CONFIG_BAT2_ACCESS_RW=y |
| 34 | CONFIG_BAT2_ICACHE_INHIBITED=y |
| 35 | CONFIG_BAT2_ICACHE_GUARDED=y |
| 36 | CONFIG_BAT2_DCACHE_INHIBITED=y |
| 37 | CONFIG_BAT2_DCACHE_GUARDED=y |
| 38 | CONFIG_BAT2_USER_MODE_VALID=y |
| 39 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y |
| 40 | CONFIG_BAT5=y |
| 41 | CONFIG_BAT5_NAME="IMMR" |
| 42 | CONFIG_BAT5_BASE=0xE0000000 |
| 43 | CONFIG_BAT5_LENGTH_256_MBYTES=y |
| 44 | CONFIG_BAT5_ACCESS_RW=y |
| 45 | CONFIG_BAT5_ICACHE_INHIBITED=y |
| 46 | CONFIG_BAT5_ICACHE_GUARDED=y |
| 47 | CONFIG_BAT5_DCACHE_INHIBITED=y |
| 48 | CONFIG_BAT5_DCACHE_GUARDED=y |
| 49 | CONFIG_BAT5_USER_MODE_VALID=y |
| 50 | CONFIG_BAT5_SUPERVISOR_MODE_VALID=y |
| 51 | CONFIG_BAT6=y |
| 52 | CONFIG_BAT6_NAME="STACK_IN_DCACHE" |
| 53 | CONFIG_BAT6_BASE=0xF0000000 |
| 54 | CONFIG_BAT6_LENGTH_256_MBYTES=y |
| 55 | CONFIG_BAT6_ACCESS_RW=y |
| 56 | CONFIG_BAT6_ICACHE_GUARDED=y |
| 57 | CONFIG_BAT6_DCACHE_GUARDED=y |
| 58 | CONFIG_BAT6_USER_MODE_VALID=y |
| 59 | CONFIG_BAT6_SUPERVISOR_MODE_VALID=y |
Mario Six | b47839c | 2019-01-21 09:17:58 +0100 | [diff] [blame] | 60 | CONFIG_NAND_LBLAWBAR_PRELIM_1=y |
| 61 | CONFIG_LBLAW0=y |
| 62 | CONFIG_LBLAW0_BASE=0xFE000000 |
| 63 | CONFIG_LBLAW0_NAME="FLASH" |
| 64 | CONFIG_LBLAW0_LENGTH_16_MBYTES=y |
| 65 | CONFIG_LBLAW1=y |
| 66 | CONFIG_LBLAW1_BASE=0xE2800000 |
| 67 | CONFIG_LBLAW1_NAME="NAND" |
| 68 | CONFIG_LBLAW1_LENGTH_32_KBYTES=y |
| 69 | CONFIG_LBLAW2=y |
| 70 | CONFIG_LBLAW2_BASE=0xF0000000 |
| 71 | CONFIG_LBLAW2_NAME="VSC7385" |
| 72 | CONFIG_LBLAW2_LENGTH_128_KBYTES=y |
| 73 | CONFIG_LBLAW3=y |
| 74 | CONFIG_LBLAW3_BASE=0xFA000000 |
| 75 | CONFIG_LBLAW3_NAME="BCSR" |
| 76 | CONFIG_LBLAW3_LENGTH_32_KBYTES=y |
Mario Six | 8b2141c | 2019-01-21 09:18:09 +0100 | [diff] [blame] | 77 | CONFIG_HID0_FINAL_EMCP=y |
| 78 | CONFIG_HID0_FINAL_DPM=y |
| 79 | CONFIG_HID0_FINAL_ICE=y |
| 80 | CONFIG_HID2_HBE=y |
Mario Six | aa50254 | 2019-01-21 09:18:12 +0100 | [diff] [blame^] | 81 | CONFIG_ACR_PIPE_DEP_4=y |
| 82 | CONFIG_ACR_RPTCNT_4=y |
Simon Glass | e3ee2fb | 2016-02-22 22:55:43 -0700 | [diff] [blame] | 83 | CONFIG_OF_BOARD_SETUP=y |
| 84 | CONFIG_OF_STDOUT_VIA_ALIAS=y |
Adam Ford | 42efb61 | 2017-08-07 17:37:18 -0400 | [diff] [blame] | 85 | CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" |
Heiko Schocher | 0b368b1 | 2016-06-07 08:31:14 +0200 | [diff] [blame] | 86 | CONFIG_BOOTDELAY=6 |
Adam Ford | 1054176 | 2018-07-29 13:13:29 -0500 | [diff] [blame] | 87 | CONFIG_MISC_INIT_R=y |
Mario Six | 75b23ed | 2018-03-28 14:38:15 +0200 | [diff] [blame] | 88 | CONFIG_BOARD_EARLY_INIT_R=y |
Tom Rini | 623d67e | 2018-02-06 12:15:38 -0500 | [diff] [blame] | 89 | # CONFIG_SPL_FRAMEWORK is not set |
Simon Goldschmidt | cc4078c | 2018-09-30 14:31:53 +0200 | [diff] [blame] | 90 | CONFIG_SPL_TEXT_BASE=0xFFF00000 |
Tom Rini | e0056d7 | 2018-06-04 11:57:37 -0400 | [diff] [blame] | 91 | CONFIG_SPL_NAND_SUPPORT=y |
Tom Rini | f852e73 | 2016-04-21 21:37:19 -0400 | [diff] [blame] | 92 | CONFIG_HUSH_PARSER=y |
Tuomas Tynkkynen | 28d56bd | 2017-10-08 21:48:01 +0300 | [diff] [blame] | 93 | CONFIG_CMD_IMLS=y |
Thomas Chou | 3a077cd | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 94 | CONFIG_CMD_GPIO=y |
Tom Rini | 78873cd | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 95 | CONFIG_CMD_I2C=y |
| 96 | CONFIG_CMD_NAND=y |
Simon Glass | c88a09a | 2017-08-04 16:34:34 -0600 | [diff] [blame] | 97 | CONFIG_CMD_PCI=y |
Joe Hershberger | 5a9d7f1 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 98 | # CONFIG_CMD_SETEXPR is not set |
Tom Rini | 0f2dcb9 | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 99 | CONFIG_CMD_DHCP=y |
Tom Rini | 1d9ac83 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 100 | CONFIG_CMD_MII=y |
Tom Rini | 0f2dcb9 | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 101 | CONFIG_CMD_PING=y |
Chris Packham | 3e257df | 2017-04-29 15:20:28 +1200 | [diff] [blame] | 102 | CONFIG_CMD_DATE=y |
Tom Rini | c20bb73 | 2017-07-22 18:36:16 -0400 | [diff] [blame] | 103 | CONFIG_CMD_MTDPARTS=y |
Tom Rini | 5ad8e11 | 2017-10-22 17:55:07 -0400 | [diff] [blame] | 104 | CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash" |
| 105 | CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" |
Maxime Ripard | 7569e18 | 2018-01-23 21:17:01 +0100 | [diff] [blame] | 106 | # CONFIG_ENV_IS_IN_FLASH is not set |
Tom Rini | 5b0b040 | 2017-08-28 07:16:32 -0400 | [diff] [blame] | 107 | CONFIG_ENV_IS_IN_NAND=y |
Tom Rini | 9834b90 | 2017-03-13 13:48:42 -0400 | [diff] [blame] | 108 | # CONFIG_MMC is not set |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 109 | CONFIG_MTD_NOR_FLASH=y |
Adam Ford | 76da1b2 | 2018-10-14 15:10:50 -0500 | [diff] [blame] | 110 | CONFIG_FLASH_CFI_DRIVER=y |
| 111 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y |
| 112 | CONFIG_SYS_FLASH_PROTECTION=y |
| 113 | CONFIG_SYS_FLASH_CFI=y |
Adam Ford | 42efb61 | 2017-08-07 17:37:18 -0400 | [diff] [blame] | 114 | CONFIG_NAND=y |
Mario Six | f504d1a | 2018-04-27 14:52:21 +0200 | [diff] [blame] | 115 | CONFIG_PHY_MARVELL=y |
Mario Six | da4fc93 | 2018-03-28 14:38:18 +0200 | [diff] [blame] | 116 | CONFIG_TSEC_ENET=y |
Thomas Chou | a6cec01 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 117 | CONFIG_SYS_NS16550=y |
Simon Glass | a66c541 | 2016-02-22 22:55:42 -0700 | [diff] [blame] | 118 | CONFIG_OF_LIBFDT=y |
Mario Six | 1faf95d | 2019-01-21 09:18:03 +0100 | [diff] [blame] | 119 | CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y |
| 120 | CONFIG_ELBC_BR0_OR0=y |
| 121 | CONFIG_BR0_OR0_NAME="NAND" |
| 122 | CONFIG_BR0_OR0_BASE=0xE2800000 |
| 123 | CONFIG_BR0_ERRORCHECKING_BOTH=y |
| 124 | CONFIG_BR0_MACHINE_FCM=y |
| 125 | CONFIG_BR0_PORTSIZE_8BIT=y |
| 126 | CONFIG_OR0_AM_32_KBYTES=y |
| 127 | CONFIG_OR0_SCY_1=y |
| 128 | CONFIG_OR0_TRLX_RELAXED=y |
| 129 | CONFIG_OR0_CHT_TWO_CLOCK=y |
| 130 | CONFIG_OR0_CSCT_8_CYCLE=y |
| 131 | CONFIG_OR0_CST_ONE_CLOCK=y |
| 132 | CONFIG_OR0_EHTR_8_CYCLE=y |
| 133 | CONFIG_ELBC_BR1_OR1=y |
| 134 | CONFIG_BR1_OR1_NAME="FLASH" |
| 135 | CONFIG_BR1_OR1_BASE=0xFE000000 |
| 136 | CONFIG_BR1_MACHINE_GPCM=y |
| 137 | CONFIG_BR1_PORTSIZE_16BIT=y |
| 138 | CONFIG_OR1_AM_8_MBYTES=y |
| 139 | CONFIG_OR1_EAD_EXTRA=y |
| 140 | CONFIG_OR1_SCY_9=y |
| 141 | CONFIG_OR1_XACS_EXTENDED=y |
| 142 | CONFIG_OR1_EHTR_1_CYCLE=y |
| 143 | CONFIG_ELBC_BR3_OR3=y |
| 144 | CONFIG_BR3_OR3_NAME="BCSR" |
| 145 | CONFIG_BR3_OR3_BASE=0xFA000000 |
| 146 | CONFIG_BR3_MACHINE_GPCM=y |
| 147 | CONFIG_BR3_PORTSIZE_8BIT=y |
| 148 | CONFIG_OR3_AM_32_KBYTES=y |
| 149 | CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y |
| 150 | CONFIG_OR3_CSNT_EARLIER=y |
| 151 | CONFIG_OR3_EAD_EXTRA=y |
| 152 | CONFIG_OR3_SCY_15=y |
| 153 | CONFIG_OR3_XACS_EXTENDED=y |
| 154 | CONFIG_OR3_TRLX_RELAXED=y |
| 155 | CONFIG_OR3_EHTR_8_CYCLE=y |
| 156 | CONFIG_ELBC_BR2_OR2=y |
| 157 | CONFIG_BR2_OR2_NAME="VSC7385" |
| 158 | CONFIG_BR2_OR2_BASE=0xF0000000 |
| 159 | CONFIG_BR2_MACHINE_GPCM=y |
| 160 | CONFIG_BR2_PORTSIZE_8BIT=y |
| 161 | CONFIG_OR2_AM_128_KBYTES=y |
| 162 | CONFIG_OR2_CSNT_EARLIER=y |
| 163 | CONFIG_OR2_EAD_EXTRA=y |
| 164 | CONFIG_OR2_SCY_15=y |
| 165 | CONFIG_OR2_SETA_EXTERNAL=y |
| 166 | CONFIG_OR2_XACS_EXTENDED=y |
| 167 | CONFIG_OR2_TRLX_RELAXED=y |
| 168 | CONFIG_OR2_EHTR_8_CYCLE=y |