blob: c49fd210883054a7dbf2a67ad7b011b6e5152b42 [file] [log] [blame]
Hou Zhiqiangfe812802019-08-20 09:35:26 +00001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * T102X Silicon/SoC Device Tree Source (pre include)
4 *
5 * Copyright 2013 Freescale Semiconductor Inc.
6 * Copyright 2019 NXP
7 */
8
9/dts-v1/;
10
11/include/ "e5500_power_isa.dtsi"
12
13/ {
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&mpic>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: PowerPC,e5500@0 {
23 device_type = "cpu";
24 reg = <0>;
25 #cooling-cells = <2>;
26 };
27 cpu1: PowerPC,e5500@1 {
28 device_type = "cpu";
29 reg = <1>;
30 #cooling-cells = <2>;
31 };
32 };
33
34 soc: soc@ffe000000 {
35 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
36 reg = <0xf 0xfe000000 0 0x00001000>;
37 #address-cells = <1>;
38 #size-cells = <1>;
39 device_type = "soc";
40 compatible = "simple-bus";
41
42 mpic: pic@40000 {
43 interrupt-controller;
44 #address-cells = <0>;
45 #interrupt-cells = <4>;
46 reg = <0x40000 0x40000>;
47 compatible = "fsl,mpic", "chrp,open-pic";
48 device_type = "open-pic";
49 clock-frequency = <0x0>;
50 };
51 };
Hou Zhiqiang943bec02019-08-27 11:03:27 +000052
53 pcie@ffe240000 {
54 compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
55 reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
56 law_trgt_if = <0>;
57 #address-cells = <3>;
58 #size-cells = <2>;
59 device_type = "pci";
60 bus-range = <0x0 0xff>;
61 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
62 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
63 };
64
65 pcie@ffe250000 {
66 compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
67 reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
68 law_trgt_if = <1>;
69 #address-cells = <3>;
70 #size-cells = <2>;
71 device_type = "pci";
72 bus-range = <0x0 0xff>;
73 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
74 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
75 };
76
77 pcie@ffe260000 {
78 compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
79 reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
80 law_trgt_if = <2>;
81 #address-cells = <3>;
82 #size-cells = <2>;
83 device_type = "pci";
84 bus-range = <0x0 0xff>;
85 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
86 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
87 };
Hou Zhiqiangfe812802019-08-20 09:35:26 +000088};