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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Christophe Leroy069fa832017-07-06 10:23:22 +02002/*
3 * (C) Copyright 2000-2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Christophe Leroy069fa832017-07-06 10:23:22 +02005 */
6
7#include <common.h>
8#include <mpc8xx.h>
9#include <asm/processor.h>
Christophe Leroy394f9b32017-07-06 10:33:13 +020010#include <asm/io.h>
Christophe Leroy069fa832017-07-06 10:23:22 +020011
12DECLARE_GLOBAL_DATA_PTR;
13
Christophe Leroy069fa832017-07-06 10:23:22 +020014/*
15 * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
16 */
Christophe Leroy48f896d2017-07-06 10:33:17 +020017int get_clocks(void)
Christophe Leroy069fa832017-07-06 10:23:22 +020018{
Christophe Leroy5c59bdf2018-03-16 17:20:33 +010019 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
Christophe Leroy394f9b32017-07-06 10:33:13 +020020 uint sccr = in_be32(&immap->im_clkrst.car_sccr);
Christophe Leroy297cbac2017-07-13 15:09:44 +020021 uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2);
22
Christophe Leroy069fa832017-07-06 10:23:22 +020023 /*
24 * If for some reason measuring the gclk frequency won't
25 * work, we return the hardwired value.
26 * (For example, the cogent CMA286-60 CPU module has no
27 * separate oscillator for PITRTCLK)
28 */
29 gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
30
31 if ((sccr & SCCR_EBDF11) == 0) {
32 /* No Bus Divider active */
33 gd->bus_clk = gd->cpu_clk;
34 } else {
35 /* The MPC8xx has only one BDF: half clock speed */
36 gd->bus_clk = gd->cpu_clk / 2;
37 }
38
Christophe Leroy297cbac2017-07-13 15:09:44 +020039 gd->arch.brg_clk = gd->cpu_clk / divider;
Christophe Leroy069fa832017-07-06 10:23:22 +020040
Christophe Leroy48f896d2017-07-06 10:33:17 +020041 return 0;
Christophe Leroy069fa832017-07-06 10:23:22 +020042}