blob: fe398a1d4965b33b2ff4e244b61e877c2913ae1f [file] [log] [blame]
Michal Simeke34f1f62016-09-19 10:41:55 +02001menu "FPGA support"
2
Siva Durga Prasad Paladugu460fdce2016-01-13 16:25:37 +05303config FPGA
4 bool
5
Patrick Bruennba81b042016-11-04 11:57:02 +01006config FPGA_ALTERA
7 bool "Enable Altera FPGA drivers"
8 select FPGA
9 help
10 Say Y here to enable the Altera FPGA driver
11
12 This provides basic infrastructure to support Altera FPGA devices.
13 Enable Altera FPGA specific functions which includes bitstream
14 (in BIT format), fpga and device validation.
15
Tien Fong Cheecde42192017-07-26 13:05:40 +080016config FPGA_SOCFPGA
17 bool "Enable Gen5 and Arria10 common FPGA drivers"
18 select FPGA_ALTERA
19 help
20 Say Y here to enable the Gen5 and Arria10 common FPGA driver
21
22 This provides common functionality for Gen5 and Arria10 devices.
23
Patrick Bruennba81b042016-11-04 11:57:02 +010024config FPGA_CYCLON2
25 bool "Enable Altera FPGA driver for Cyclone II"
26 depends on FPGA_ALTERA
27 help
28 Say Y here to enable the Altera Cyclone II FPGA specific driver
29
30 This provides common functionality for Altera Cyclone II devices.
31 Enable FPGA driver for loading bitstream in BIT and BIN format
32 on Altera Cyclone II device.
33
Ang, Chee Hongdcc3bb62018-12-19 18:35:14 -080034config FPGA_STRATIX10
35 bool "Enable Altera FPGA driver for Stratix 10"
36 depends on TARGET_SOCFPGA_STRATIX10
37 select FPGA_ALTERA
38 help
39 Say Y here to enable the Altera Stratix 10 FPGA specific driver
40
41 This provides common functionality for Altera Stratix 10 devices.
42 Enable FPGA driver for writing bitstream into Altera Stratix10
43 device.
44
Siva Durga Prasad Paladugu460fdce2016-01-13 16:25:37 +053045config FPGA_XILINX
46 bool "Enable Xilinx FPGA drivers"
47 select FPGA
48 help
49 Enable Xilinx FPGA specific functions which includes bitstream
50 (in BIT format), fpga and device validation.
51
52config FPGA_ZYNQMPPL
53 bool "Enable Xilinx FPGA driver for ZynqMP"
54 depends on FPGA_XILINX
55 help
56 Enable FPGA driver for loading bitstream in BIT and BIN format
57 on Xilinx Zynq UltraScale+ (ZynqMP) device.
58
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053059config FPGA_VERSALPL
60 bool "Enable Xilinx FPGA driver for Versal"
61 depends on FPGA_XILINX
62 help
63 Enable FPGA driver for loading bitstream in PDI format on Xilinx
64 Versal device. PDI is a new programmable device image format for
65 Versal. The bitstream will only be generated as PDI for Versal
66 platform.
67
Vipul Kumarb8f64b92018-02-16 18:02:49 +053068config FPGA_SPARTAN3
Michal Simek55af55a2018-07-23 15:59:55 +020069 bool "Enable Spartan3 FPGA driver"
Robert Hancockbe7f7462019-06-18 09:47:13 -060070 depends on FPGA_XILINX
Michal Simek55af55a2018-07-23 15:59:55 +020071 help
72 Enable Spartan3 FPGA driver for loading in BIT format.
Vipul Kumarb8f64b92018-02-16 18:02:49 +053073
Robert Hancockbe7f7462019-06-18 09:47:13 -060074config FPGA_VIRTEX2
75 bool "Enable Xilinx Virtex-II and later FPGA driver"
76 depends on FPGA_XILINX
77 help
78 Enable Virtex-II FPGA driver for loading in BIT format. This driver
79 also supports many newer Xilinx FPGA families.
80
Vipul Kumar4a4946b2018-02-16 18:02:51 +053081config FPGA_ZYNQPL
Michal Simek55af55a2018-07-23 15:59:55 +020082 bool "Enable Xilinx FPGA for Zynq"
83 depends on ARCH_ZYNQ
84 help
85 Enable FPGA driver for loading bitstream in BIT and BIN format
86 on Xilinx Zynq devices.
Vipul Kumar4a4946b2018-02-16 18:02:51 +053087
Michal Simeke34f1f62016-09-19 10:41:55 +020088endmenu