| Heiko Schocher | f853c6c | 2014-07-18 06:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Boundary Devices |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | /* ZQ Calibration */ |
| 7 | DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 |
| 8 | DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003 |
| 9 | DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F |
| 10 | DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F |
| 11 | DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F |
| 12 | DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F |
| 13 | /* |
| 14 | * DQS gating, read delay, write delay calibration values |
| 15 | * based on calibration compare of 0x00ffff00 |
| 16 | */ |
| 17 | DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E |
| 18 | DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200 |
| 19 | DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202 |
| 20 | DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172 |
| 21 | DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C |
| 22 | DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49 |
| 23 | DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133 |
| 24 | DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E |
| 25 | /* read data bit delay */ |
| 26 | DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 |
| 27 | DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 |
| 28 | DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 |
| 29 | DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 |
| 30 | DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 |
| 31 | DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 |
| 32 | DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 |
| 33 | DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 |
| 34 | /* Complete calibration by forced measurment */ |
| 35 | DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 |
| 36 | DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 |
| 37 | /* in DDR3, 64-bit mode, only MMDC0 is initiated */ |
| 38 | DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d |
| 39 | DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 |
| 40 | DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323 |
| 41 | DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63 |
| 42 | DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db |
| 43 | DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 |
| 44 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 |
| 45 | DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 |
| 46 | DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21 |
| 47 | DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 |
| 48 | DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 |
| 49 | /* MR2 */ |
| 50 | DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 |
| 51 | DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a |
| 52 | /* MR3 */ |
| 53 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 |
| 54 | DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b |
| 55 | /* MR1 */ |
| 56 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 |
| 57 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 |
| 58 | /* MR0 */ |
| 59 | DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030 |
| 60 | DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038 |
| 61 | /* ZQ calibration */ |
| 62 | DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 |
| 63 | DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 |
| 64 | /* final ddr setup */ |
| 65 | DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 |
| 66 | DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 |
| 67 | DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007 |
| 68 | DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d |
| 69 | DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006 |
| 70 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 |