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git01.mediatek.com / filogic / uboot / a9b9ed4f6936cee60bec86a9409d9cc2c255634a / . / drivers / ram / starfive / ddrphy_start.c
blob: 479b6ef10418d250031030d59a926a8fad65ce91 [file] [log] [blame]
Yanhong Wangd60e8802023-03-29 11:42:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
5 */
6
7#include <common.h>
8#include <asm/io.h>
9
10#include "starfive_ddr.h"
11
12static const struct ddr_reg_cfg ddr_start_cfg[] = {
13 {89, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
14 {78, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
15 {345, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
16 {334, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
17 {601, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
18 {590, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
19 {857, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
20 {846, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
21 {1793, 0xfffffeff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
22 {1793, 0xfffcffff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
23 {125, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
24 {102, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
25 {105, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
26 {92, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
27 {94, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
28 {96, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
29 {89, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
30 {381, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
31 {358, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
32 {361, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
33 {348, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
34 {350, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
35 {352, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
36 {345, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
37 {637, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
38 {614, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
39 {617, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
40 {604, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
41 {606, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
42 {608, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
43 {601, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
44 {893, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
45 {870, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
46 {873, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
47 {860, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
48 {862, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
49 {864, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
50 {857, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
51 {1895, 0xffffe000, 0x00001342, (OFFSET_SEL | REGCLRSETALL)},
52 {1835, 0xfffff0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
53 {1793, 0xfffffeff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
54 {62, 0xfffffeff, 0x0, REGCLRSETALL},
55 {66, 0xfffffeff, 0x0, REGCLRSETALL},
56 {166, 0xffffff80, 0x00000001, REGCLRSETALL},
57 {62, 0xfff0ffff, 0x00010000, REGCLRSETALL},
58 {62, 0xf0ffffff, 0x01000000, REGCLRSETALL},
59 {166, 0xffff80ff, 0x00000100, REGCLRSETALL},
60 {179, 0xff80ffff, 0x00010000, REGCLRSETALL},
61 {67, 0xffe0ffff, 0x00010000, REGCLRSETALL},
62 {67, 0xe0ffffff, 0x01000000, REGCLRSETALL},
63 {179, 0x80ffffff, 0x01000000, REGCLRSETALL},
64 {166, 0xff80ffff, 0x00010000, REGCLRSETALL},
65 {62, 0xfff0ffff, 0x00010000, REGCLRSETALL},
66 {62, 0xf0ffffff, 0x01000000, REGCLRSETALL},
67 {166, 0x80ffffff, 0x01000000, REGCLRSETALL},
68 {182, 0xff80ffff, 0x00010000, REGCLRSETALL},
69 {67, 0xffe0ffff, 0x00010000, REGCLRSETALL},
70 {67, 0xe0ffffff, 0x01000000, REGCLRSETALL},
71 {182, 0x80ffffff, 0x01000000, REGCLRSETALL},
72 {167, 0xffffff80, 0x00000017, REGCLRSETALL},
73 {62, 0xfff0ffff, 0x00010000, REGCLRSETALL},
74 {62, 0xf0ffffff, 0x01000000, REGCLRSETALL},
75 {167, 0xffff80ff, 0x00001700, REGCLRSETALL},
76 {185, 0xff80ffff, 0x00200000, REGCLRSETALL},
77 {67, 0xffe0ffff, 0x00010000, REGCLRSETALL},
78 {67, 0xe0ffffff, 0x01000000, REGCLRSETALL},
79 {185, 0x80ffffff, 0x20000000, REGCLRSETALL},
80 {10, 0xffffffe0, 0x00000002, REGCLRSETALL},
81 {0, 0xfffffffe, 0x00000001, REGCLRSETALL},
82 {11, 0xfffffff0, 0x00000005, (F_CLRSET | REG2G)},
83 {247, 0xffffffff, 0x00000008, REGCLRSETALL},
84 {249, 0xffffffff, 0x00000800, REGCLRSETALL},
85 {252, 0xffffffff, 0x00000008, REGCLRSETALL},
86 {254, 0xffffffff, 0x00000800, REGCLRSETALL},
87 {281, 0xffffffff, 0x33000000, REGCLRSETALL},
88 {305, 0xffffffff, 0x33000000, REGCLRSETALL},
89 {329, 0xffffffff, 0x33000000, REGCLRSETALL},
90 {353, 0xffffffff, 0x33000000, REGCLRSETALL},
91 {289, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
92 {313, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
93 {337, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
94 {361, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
95 {289, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
96 {313, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
97 {337, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
98 {361, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
99 {282, 0xffffffff, 0x00160000, REGCLRSETALL},
100 {306, 0xffffffff, 0x00160000, REGCLRSETALL},
101 {330, 0xffffffff, 0x00160000, REGCLRSETALL},
102 {354, 0xffffffff, 0x00160000, REGCLRSETALL},
103 {290, 0xffffffff, 0x00160000, REGCLRSETALL},
104 {314, 0xffffffff, 0x00160000, REGCLRSETALL},
105 {338, 0xffffffff, 0x00160000, REGCLRSETALL},
106 {362, 0xffffffff, 0x00160000, REGCLRSETALL},
107 {282, 0xffffff00, 0x17, REGCLRSETALL},
108 {306, 0xffffff00, 0x17, REGCLRSETALL},
109 {330, 0xffffff00, 0x17, REGCLRSETALL},
110 {354, 0xffffff00, 0x17, REGCLRSETALL},
111 {290, 0xffffff00, 0x17, REGCLRSETALL},
112 {314, 0xffffff00, 0x17, REGCLRSETALL},
113 {338, 0xffffff00, 0x17, REGCLRSETALL},
114 {362, 0xffffff00, 0x17, REGCLRSETALL},
115 {282, 0xffff00ff, 0x2000, REGCLRSETALL},
116 {306, 0xffff00ff, 0x2000, REGCLRSETALL},
117 {330, 0xffff00ff, 0x2000, REGCLRSETALL},
118 {354, 0xffff00ff, 0x2000, REGCLRSETALL},
119 {290, 0xffff00ff, 0x2000, REGCLRSETALL},
120 {314, 0xffff00ff, 0x2000, REGCLRSETALL},
121 {338, 0xffff00ff, 0x2000, REGCLRSETALL},
122 {362, 0xffff00ff, 0x2000, REGCLRSETALL},
123 {65, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
124 {321, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
125 {577, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
126 {833, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
127 {96, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
128 {352, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
129 {608, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
130 {864, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
131 {96, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
132 {352, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
133 {608, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
134 {864, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
135 {33, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
136 {289, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
137 {545, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
138 {801, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
139 {1038, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)},
140 {1294, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)},
141 {1550, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)},
142 {83, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
143 {339, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
144 {595, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
145 {851, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
146 {1062, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
147 {1318, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
148 {1574, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
149 {1892, 0xfffc0000, 0x15547, (OFFSET_SEL | REGCLRSETALL)},
150 {1893, 0xfffc0000, 0x7, (OFFSET_SEL | REGCLRSETALL)},
151 {1852, 0xffffe000, 0x07a, (OFFSET_SEL | REGCLRSETALL)},
152 {1853, 0xffffffff, 0x0100, (OFFSET_SEL | REGCLRSETALL)},
153 {1822, 0xffffffff, 0xFF, (OFFSET_SEL | REGCLRSETALL)},
154 {1896, 0xfffffc00, 0x03d5, (OFFSET_SEL | REGCLRSETALL)},
155 {91, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
156 {347, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
157 {603, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
158 {859, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
159 {1912, 0x0, 0xcc3bfc7, (OFFSET_SEL | REGSETALL)},
160 {1913, 0x0, 0xff8f, (OFFSET_SEL | REGSETALL)},
161 {1914, 0x0, 0x33f07ff, (OFFSET_SEL | REGSETALL)},
162 {1915, 0x0, 0xc3c37ff, (OFFSET_SEL | REGSETALL)},
163 {1916, 0x0, 0x1fffff10, (OFFSET_SEL | REGSETALL)},
164 {1917, 0x0, 0x230070, (OFFSET_SEL | REGSETALL)},
165 {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG4G | REG2G | F_SET)},
166 {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG8G | F_SET)},
167 {1919, 0x0, 0xe10, (OFFSET_SEL | REGSETALL)},
168 {1920, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
169 {1921, 0x0, 0x188411, (OFFSET_SEL | REGSETALL)},
170 {1922, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
171 {1923, 0x0, 0x180400, (OFFSET_SEL | REGSETALL)},
172 {1924, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
173 {1925, 0x0, 0x180400, (OFFSET_SEL | REGSETALL)},
174 {1926, 0x0, 0x1fffffcf, (OFFSET_SEL | REGSETALL)},
175 {1927, 0x0, 0x188400, (OFFSET_SEL | REGSETALL)},
176 {1928, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
177 {1929, 0x0, 0x4188411, (OFFSET_SEL | REGSETALL)},
178 {1837, 0x0, 0x24410, (OFFSET_SEL | REGSETALL)},
179 {1840, 0x0, 0x24410, (OFFSET_SEL | REGSETALL)},
180 {1842, 0x0, 0x2ffff, (OFFSET_SEL | REGSETALL)},
181 {76, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
182 {332, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
183 {588, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
184 {844, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
185 {77, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
186 {333, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
187 {589, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
188 {845, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
189 {1062, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
190 {1318, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
191 {1574, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
192 {1062, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
193 {1318, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
194 {1574, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
195 {1028, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)},
196 {1284, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)},
197 {1540, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)},
198 {1848, 0x0, 0x3cf07f8, (OFFSET_SEL | REGSETALL)},
199 {1849, 0x0, 0x3f, (OFFSET_SEL | REGSETALL)},
200 {1850, 0x0, 0x1fffff, (OFFSET_SEL | REGSETALL)},
201 {1851, 0x0, 0x060000, (OFFSET_SEL | REGSETALL)},
202 {130, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
203 {386, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
204 {642, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
205 {898, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
206 {131, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
207 {387, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
208 {643, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
209 {899, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
210 {29, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
211 {285, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
212 {541, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
213 {797, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
214 {30, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
215 {286, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
216 {542, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
217 {798, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
218 {31, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
219 {287, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
220 {543, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
221 {799, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
222 {1071, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
223 {1327, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
224 {1583, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
225 {1808, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
226 {1896, 0xfff0ffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
227};
228
229void ddr_reg_set(u32 *reg, const struct ddr_reg_cfg *data,
230 u32 len, u32 mask)
231{
232 u32 *addr;
233 u32 i;
234
235 for (i = 0; i < len; i++) {
236 if (!(data[i].flag & mask))
237 continue;
238
239 if (data[i].flag & OFFSET_SEL)
240 addr = reg + PHY_AC_BASE_ADDR + data[i].offset;
241 else
242 addr = reg + PHY_BASE_ADDR + data[i].offset;
243
244 if (data[i].flag & F_CLRSET)
245 DDR_REG_TRIGGER(addr, data[i].mask, data[i].val);
246 else if (data[i].flag & F_SET)
247 out_le32(addr, data[i].val);
248 else
249 out_le32(addr, in_le32(addr) + data[i].val);
250 }
251}
252
253void ddr_phy_start(u32 *phyreg, enum ddr_size_t size)
254{
255 u32 len;
256 u32 mask;
257
258 switch (size) {
259 case DDR_SIZE_2G:
260 mask = REG2G;
261 break;
262
263 case DDR_SIZE_4G:
264 mask = REG4G;
265 break;
266
267 case DDR_SIZE_8G:
268 mask = REG8G;
269 break;
270
271 case DDR_SIZE_16G:
272 default:
273 return;
274 };
275
276 len = ARRAY_SIZE(ddr_start_cfg);
277 ddr_reg_set(phyreg, ddr_start_cfg, len, mask);
278 out_le32(phyreg, 0x01);
279}