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git01.mediatek.com / filogic / uboot / a9b24dbbc93fade411994128fea6152039e9001c / . / arch / arm / mach-rmobile / include / mach / r8a7740.h
blob: 989da337fec9ae0b78178c0d60268799750f323e [file] [log] [blame]
Nobuhiro Iwamatsu3966dea2012-07-20 13:06:54 +0900[diff] [blame]1/*
2 * Copyright (C) 2012 Renesas Solutions Corp.
3 *
Tom Rinie2378802016-01-14 22:05:13 -0500[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0
Nobuhiro Iwamatsu3966dea2012-07-20 13:06:54 +0900[diff] [blame]5 */
6
7#ifndef __ASM_ARCH_R8A7740_H
8#define __ASM_ARCH_R8A7740_H
9
10/*
11 * R8A7740 I/O Addresses
12 */
13
14#define MERAM_BASE 0xE5580000
15#define DDRP_BASE 0xC12A0000
16#define HPB_BASE 0xE6000000
17#define RWDT0_BASE 0xE6020000
18#define RWDT1_BASE 0xE6030000
19#define GPIO_BASE 0xE6050000
20#define CMT1_BASE 0xE6138000
21#define CPG_BASE 0xE6150000
22#define SYSC_BASE 0xE6180000
23#define SDHI0_BASE 0xE6850000
24#define SDHI1_BASE 0xE6860000
25#define MMCIF_BASE 0xE6BD0000
26#define SCIF5_BASE 0xE6CB0000
27#define SCIF6_BASE 0xE6CC0000
28#define DBSC_BASE 0xFE400000
29#define BSC_BASE 0xFEC10000
30#define I2C0_BASE 0xFFF20000
31#define I2C1_BASE 0xE6C20000
32#define TMU_BASE 0xFFF80000
33
34#ifndef __ASSEMBLY__
35#include <asm/types.h>
36
37/* RWDT */
38struct r8a7740_rwdt {
39 u16 rwtcnt0; /* 0x00 */
40 u16 dummy0; /* 0x02 */
41 u16 rwtcsra0; /* 0x04 */
42 u16 dummy1; /* 0x06 */
43 u16 rwtcsrb0; /* 0x08 */
44 u16 dummy2; /* 0x0A */
45};
46
47/* HPB Semaphore Control Registers */
48struct r8a7740_hpb {
49 u32 hpbctrl0;
50 u32 hpbctrl1;
51 u32 hpbctrl2;
52 u32 cccr;
53 u32 dummy0; /* 0x20 */
54 u32 hpbctrl4;
55 u32 hpbctrl5;
56};
57
58/* CPG */
59struct r8a7740_cpg {
60 u32 frqcra;
61 u32 frqcrb;
62 u32 vclkcr1;
63 u32 vclkcr2;
64 u32 fmsickcr;
65 u32 fmsockcr;
66 u32 fsiackcr;
67 u32 dummy0; /* 0x1c */
68 u32 rtstbcr;
69 u32 systbcr;
70 u32 pllc01cr;
71 u32 pllc2cr;
72 u32 mstpsr0;
73 u32 dummy1; /* 0x34 */
74 u32 mstpsr1;
75 u32 mstpsr5;
76 u32 mstpsr2;
77 u32 dummy2; /* 0x44 */
78 u32 mstpsr3;
79 u32 mstpsr4;
80 u32 dummy3; /* 0x50 */
81 u32 astat;
82 u32 dummy4[4]; /* 0x58 .. 0x64 */
83 u32 ztrckcr;
84 u32 dummy5[5]; /* 0x6c .. 0x7c */
85 u32 subckcr;
86 u32 spuckcr;
87 u32 vouckcr;
88 u32 usbckcr;
89 u32 dummy6[3]; /* 0x90 .. 0x98 */
90 u32 stprckcr;
91 u32 srcr0;
92 u32 dummy7; /* 0xa4 */
93 u32 srcr1;
94 u32 dummy8; /* 0xac */
95 u32 srcr2;
96 u32 dummy9; /* 0xb4 */
97 u32 srcr3;
98 u32 srcr4;
99 u32 dummy10; /* 0xc0 */
100 u32 srcr5;
101 u32 pllc01stpcr;
102 u32 dummy11[5]; /* 0xcc .. 0xdc */
103 u32 frqcrc;
104 u32 frqcrd;
105 u32 dummy12[10]; /* 0xe8 .. 0x10c */
106 u32 rmstpcr0;
107 u32 rmstpcr1;
108 u32 rmstpcr2;
109 u32 rmstpcr3;
110 u32 rmstpcr4;
111 u32 rmstpcr5;
112 u32 dummy13[2]; /* 0x128 .. 0x12c */
113 u32 smstpcr0;
114 u32 smstpcr1;
115 u32 smstpcr2;
116 u32 smstpcr3;
117 u32 smstpcr4;
118 u32 smstpcr5;
119};
120
121/* BSC */
122struct r8a7740_bsc {
123 u32 cmncr;
124 u32 cs0bcr;
125 u32 cs2bcr;
126 u32 dummy0; /* 0x0c */
127 u32 cs4bcr;
128 u32 cs5abcr;
129 u32 cs5bbcr;
130 u32 cs6abcr;
131 u32 dummy1; /* 0x20 */
132 u32 cs0wcr;
133 u32 cs2wcr;
134 u32 dummy2; /* 0x2c */
135 u32 cs4wcr;
136 u32 cs5awcr;
137 u32 cs5bwcr;
138 u32 cs6awcr;
139 u32 dummy3[5]; /* 0x40 .. 0x50 */
140 u32 rbwtcnt;
141 u32 busycr;
142 u32 dummy4[5]; /* 0x5c .. 0x6c */
143 u32 bromtimcr;
144 u32 dummy5[7]; /* 0x74 .. 0x8c */
145 u32 bptcr00;
146 u32 bptcr01;
147 u32 bptcr02;
148 u32 bptcr03;
149 u32 bptcr04;
150 u32 bptcr05;
151 u32 bptcr06;
152 u32 bptcr07;
153 u32 bptcr08;
154 u32 bptcr09;
155 u32 bptcr10;
156 u32 bptcr11;
157 u32 bptcr12;
158 u32 bptcr13;
159 u32 bptcr14;
160 u32 bptcr15;
161 u32 bptcr16;
162 u32 bptcr17;
163 u32 bptcr18;
164 u32 bptcr19;
165 u32 bptcr20;
166 u32 bptcr21;
167 u32 bptcr22;
168 u32 bptcr23;
169 u32 bptcr24;
170 u32 bptcr25;
171 u32 bptcr26;
172 u32 bptcr27;
173 u32 bptcr28;
174 u32 bptcr29;
175 u32 bptcr30;
176 u32 bptcr31;
177 u32 bswcr;
178 u32 dummy6[68]; /* 0x114 .. 0x220 */
179 u32 cs0wcr2;
180 u32 cs2wcr2;
181 u32 dummy7; /* 0x22c */
182 u32 cs4wcr2;
183};
184
185#define CS0WCR2 0xFEC10224
186#define CS2WCR2 0xFEC10228
187#define CS4WCR2 0xFEC10230
188
189/* DDRP */
190struct r8a7740_ddrp {
191 u32 funcctrl;
192 u32 dllctrl;
193 u32 zqcalctrl;
194 u32 zqodtctrl;
195 u32 rdctrl;
196 u32 rdtmg;
197 u32 fifoinit;
198 u32 outctrl;
199 u32 dummy0[50]; /* 0x20 .. 0xe4 */
200 u32 dqcalofs1;
201 u32 dqcalofs2;
202 u32 dummy1[2]; /* 0xf0 .. 0xf4 */
203 u32 dqcalexp;
204};
205
206#define DDRPNCNT 0xE605803C
207#define DDRVREFCNT 0xE61500EC
208
209/* DBSC */
210struct r8a7740_dbsc {
211 u32 dummy0;
212 u32 dbsvcr;
213 u32 dbstate0;
214 u32 dbstate1;
215 u32 dbacen;
216 u32 dbrfen;
217 u32 dbcmd;
218 u32 dbwait;
219 u32 dbkind;
220 u32 dbconf0;
221 u32 dummy1[2]; /* 0x28 .. 0x2c */
222 u32 dbphytype;
223 u32 dummy2[3]; /* 0x34 .. 0x3c */
224 u32 dbtr0;
225 u32 dbtr1;
226 u32 dbtr2;
227 u32 dummy3; /* 0x4c */
228 u32 dbtr3;
229 u32 dbtr4;
230 u32 dbtr5;
231 u32 dbtr6;
232 u32 dbtr7;
233 u32 dbtr8;
234 u32 dbtr9;
235 u32 dbtr10;
236 u32 dbtr11;
237 u32 dbtr12;
238 u32 dbtr13;
239 u32 dbtr14;
240 u32 dbtr15;
241 u32 dbtr16;
242 u32 dbtr17;
243 u32 dbtr18;
244 u32 dbtr19;
245 u32 dummy4[7]; /* 0x94 .. 0xac */
246 u32 dbbl;
247 u32 dummy5[3]; /* 0xb4 .. 0xbc */
248 u32 dbadj0;
249 u32 dbadj1;
250 u32 dbadj2;
251 u32 dummy6[5]; /* 0xcc .. 0xdc */
252 u32 dbrfcnf0;
253 u32 dbrfcnf1;
254 u32 dbrfcnf2;
255 u32 dbrfcnf3;
256 u32 dummy7; /* 0xf0 */
257 u32 dbcalcnf;
258 u32 dbcaltr;
259 u32 dummy8; /* 0xfc */;
260 u32 dbrnk0;
261 u32 dummy9[31]; /* 0x104 .. 0x17C */
262 u32 dbpdncnf;
263 u32 dummy10[7]; /* 0x184 .. 0x19C */
264 u32 dbmrrdr;
265 u32 dummy11[39]; /* 0x1A4 .. 0x23C */
266 u32 dbdfistat;
267 u32 dbdficnt;
268 u32 dummy12[46]; /* 0x248 .. 0x2FC */
269 u32 dbbs0cnt0;
270 u32 dbbs0cnt1;
271};
272
273#endif
274
275#endif /* __ASM_ARCH_R8A7740_H */