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git01.mediatek.com / filogic / uboot / a9ad45945bb4fb1c5ae11f40652676b17bb7871d / . / include / configs / canyonlands.h
blob: e244c8725b49df0f0fc803291ac6929d0297a158 [file] [log] [blame]
Stefan Roesea9ad4592008-03-11 16:52:24 +0100[diff] [blame^]1/*
2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21/************************************************************************
22 * canyonlands.h - configuration for Canyonlands (460EX)
23 ***********************************************************************/
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*-----------------------------------------------------------------------
28 * High Level Configuration Options
29 *----------------------------------------------------------------------*/
30#define CONFIG_CANYONLANDS 1 /* Board is Canyonlands */
31#define CONFIG_440 1
32#define CONFIG_4xx 1 /* ... PPC4xx family */
33#define CONFIG_460EX 1 /* Specific PPC460EX support */
34
35#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
36
37#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
38#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
39#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
40
41/*-----------------------------------------------------------------------
42 * Base addresses -- Note these are effective addresses where the
43 * actual resources get mapped (not physical addresses)
44 *----------------------------------------------------------------------*/
45#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
46
47#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
48#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
49#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
50
51#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
52#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
53#define CFG_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
54
55#define CFG_PCIE0_CFGBASE 0xc0000000
56#define CFG_PCIE1_CFGBASE 0xc1000000
57#define CFG_PCIE0_XCFGBASE 0xc3000000
58#define CFG_PCIE1_XCFGBASE 0xc3001000
59
60#define CFG_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
61
62/* base address of inbound PCIe window */
63#define CFG_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
64
65/* EBC stuff */
66#define CFG_NAND_ADDR 0xE0000000
67#define CFG_BCSR_BASE 0xE1000000
68#define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
69#define CFG_FLASH_BASE 0xFC000000 /* later mapped to this addr */
70#define CFG_FLASH_BASE_PHYS_H 0x4
71#define CFG_FLASH_BASE_PHYS_L 0xCC000000
72#define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \
73 (u64)CFG_FLASH_BASE_PHYS_L)
74#define CFG_FLASH_SIZE (64 << 20)
75
76#define CFG_OCM_BASE 0xE3000000 /* OCM: 16k */
77#define CFG_SRAM_BASE 0xE8000000 /* SRAM: 256k */
78#define CFG_LOCAL_CONF_REGS 0xEF000000
79
80#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */
81
82#define CFG_MONITOR_BASE TEXT_BASE
83#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
84#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc()*/
85
86/*-----------------------------------------------------------------------
87 * Initial RAM & stack pointer (placed in OCM)
88 *----------------------------------------------------------------------*/
89#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
90#define CFG_INIT_RAM_END (4 << 10)
91#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
92#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
93#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
94
95/*-----------------------------------------------------------------------
96 * Serial Port
97 *----------------------------------------------------------------------*/
98#define CONFIG_BAUDRATE 115200
99#define CONFIG_SERIAL_MULTI 1
100#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
101
102#define CFG_BAUDRATE_TABLE \
103 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
104
105/*-----------------------------------------------------------------------
106 * Environment
107 *----------------------------------------------------------------------*/
108/*
109 * Define here the location of the environment variables (FLASH).
110 */
111#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
112#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
113#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
114#else
115#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
116#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
117#endif
118
119/*-----------------------------------------------------------------------
120 * FLASH related
121 *----------------------------------------------------------------------*/
122#define CFG_FLASH_CFI /* The flash is CFI compatible */
123#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
124#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
125
126#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
127#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
128#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
129
130#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
131#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
132
133#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
134#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
135
136#ifdef CFG_ENV_IS_IN_FLASH
137#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
138#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
139#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
140
141/* Address and size of Redundant Environment Sector */
142#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
143#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
144#endif /* CFG_ENV_IS_IN_FLASH */
145
146/*-----------------------------------------------------------------------
147 * NAND-FLASH related
148 *----------------------------------------------------------------------*/
149#define CFG_MAX_NAND_DEVICE 1
150#define NAND_MAX_CHIPS 1
151#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
152#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
153
154/*------------------------------------------------------------------------------
155 * DDR SDRAM
156 *----------------------------------------------------------------------------*/
157#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
158#define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
159#define CONFIG_DDR_ECC 1 /* with ECC support */
160#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
161
162/*-----------------------------------------------------------------------
163 * I2C
164 *----------------------------------------------------------------------*/
165#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
166#undef CONFIG_SOFT_I2C /* I2C bit-banged */
167#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
168#define CFG_I2C_SLAVE 0x7F
169
170#define CFG_I2C_MULTI_EEPROMS
171#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
172#define CFG_I2C_EEPROM_ADDR_LEN 1
173#define CFG_EEPROM_PAGE_WRITE_ENABLE
174#define CFG_EEPROM_PAGE_WRITE_BITS 3
175#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
176
177/* I2C SYSMON (LM75, AD7414 is almost compatible) */
178#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
179#define CONFIG_DTT_AD7414 1 /* use AD7414 */
180#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
181#define CFG_DTT_MAX_TEMP 70
182#define CFG_DTT_LOW_TEMP -30
183#define CFG_DTT_HYSTERESIS 3
184
185/* RTC configuration */
186#define CONFIG_RTC_M41T62 1
187#define CFG_I2C_RTC_ADDR 0x68
188
189/*-----------------------------------------------------------------------
190 * Ethernet
191 *----------------------------------------------------------------------*/
192#define CONFIG_IBM_EMAC4_V4 1
193#define CONFIG_MII 1 /* MII PHY management */
194#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
195#define CONFIG_PHY1_ADDR 1
196#define CONFIG_HAS_ETH0 1
197#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
198#define CONFIG_NET_MULTI 1
199
200#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
201#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
202#define CONFIG_PHY_DYNAMIC_ANEG 1
203
204#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
205
206#define CONFIG_PREBOOT "echo;" \
207 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
208 "echo"
209
210#undef CONFIG_BOOTARGS
211
212#define CONFIG_EXTRA_ENV_SETTINGS \
213 "netdev=eth0\0" \
214 "hostname=canyonlands\0" \
215 "nfsargs=setenv bootargs root=/dev/nfs rw " \
216 "nfsroot=${serverip}:${rootpath}\0" \
217 "ramargs=setenv bootargs root=/dev/ram rw\0" \
218 "addip=setenv bootargs ${bootargs} " \
219 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
220 ":${hostname}:${netdev}:off panic=1\0" \
221 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
222 "net_nfs=tftp 200000 ${bootfile};" \
223 "run nfsargs addip addtty;" \
224 "bootm 200000\0" \
225 "net_nfs_fdt=tftp 200000 ${bootfile};" \
226 "tftp ${fdt_addr} ${fdt_file};" \
227 "run nfsargs addip addtty;" \
228 "bootm 200000 - ${fdt_addr}\0" \
229 "flash_nfs=run nfsargs addip addtty;" \
230 "bootm ${kernel_addr}\0" \
231 "flash_self=run ramargs addip addtty;" \
232 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
233 "rootpath=/opt/eldk/ppc_4xxFP\0" \
234 "bootfile=canyonlands/uImage\0" \
235 "fdt_file=canyonlands/canyonlands.dtb\0" \
236 "fdt_addr=400000\0" \
237 "kernel_addr=fc000000\0" \
238 "ramdisk_addr=fc200000\0" \
239 "initrd_high=30000000\0" \
240 "load=tftp 200000 canyonlands/u-boot.bin\0" \
241 "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
242 "cp.b ${fileaddr} fffa0000 ${filesize};" \
243 "setenv filesize;saveenv\0" \
244 "upd=run load update\0" \
245 "nload=tftp 200000 canyonlands/u-boot-nand.bin\0" \
246 "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
247 "setenv filesize;saveenv\0" \
248 "nupd=run nload nupdate\0" \
249 "pciconfighost=1\0" \
250 "pcie_mode=RP:RP\0" \
251 ""
252#define CONFIG_BOOTCOMMAND "run flash_self"
253
254#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
255
256#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
257#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
258
259/*
260 * BOOTP options
261 */
262#define CONFIG_BOOTP_BOOTFILESIZE
263#define CONFIG_BOOTP_BOOTPATH
264#define CONFIG_BOOTP_GATEWAY
265#define CONFIG_BOOTP_HOSTNAME
266#define CONFIG_BOOTP_SUBNETMASK
267
268/*
269 * Command line configuration.
270 */
271#include <config_cmd_default.h>
272
273#define CONFIG_CMD_ASKENV
274#define CONFIG_CMD_DATE
275#define CONFIG_CMD_DHCP
276#define CONFIG_CMD_DTT
277#define CONFIG_CMD_DIAG
278#define CONFIG_CMD_EEPROM
279#define CONFIG_CMD_ELF
280#define CONFIG_CMD_FAT
281#define CONFIG_CMD_I2C
282#define CONFIG_CMD_IRQ
283#define CONFIG_CMD_MII
284#define CONFIG_CMD_NAND
285#define CONFIG_CMD_NET
286#define CONFIG_CMD_NFS
287#define CONFIG_CMD_PCI
288#define CONFIG_CMD_PING
289#define CONFIG_CMD_REGINFO
290#define CONFIG_CMD_SDRAM
291
292/*-----------------------------------------------------------------------
293 * Miscellaneous configurable options
294 *----------------------------------------------------------------------*/
295#define CFG_LONGHELP /* undef to save memory */
296#define CFG_PROMPT "=> " /* Monitor Command Prompt */
297#if defined(CONFIG_CMD_KGDB)
298#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
299#else
300#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
301#endif
302#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
303#define CFG_MAXARGS 16 /* max number of command args */
304#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
305
306#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
307#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
308
309#define CFG_LOAD_ADDR 0x100000 /* default load address */
310#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
311
312#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
313
314#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
315#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
316#define CONFIG_LOOPW 1 /* enable loopw command */
317#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
318#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
319#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
320#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
321
322#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
323#ifdef CFG_HUSH_PARSER
324#define CFG_PROMPT_HUSH_PS2 "> "
325#endif
326
327/*-----------------------------------------------------------------------
328 * PCI stuff
329 *----------------------------------------------------------------------*/
330/* General PCI */
331#define CONFIG_PCI /* include pci support */
332#define CONFIG_PCI_PNP /* do pci plug-and-play */
333#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
334#define CONFIG_PCI_CONFIG_HOST_BRIDGE
335
336/* Board-specific PCI */
337#define CFG_PCI_TARGET_INIT /* let board init pci target */
338#undef CFG_PCI_MASTER_INIT
339
340#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
341#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
342
343/*
344 * For booting Linux, the board info and command line data
345 * have to be in the first 8 MB of memory, since this is
346 * the maximum mapped by the Linux kernel during initialization.
347 */
348#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
349
350/*
351 * Internal Definitions
352 */
353#if defined(CONFIG_CMD_KGDB)
354#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
355#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
356#endif
357
358/*-----------------------------------------------------------------------
359 * External Bus Controller (EBC) Setup
360 *----------------------------------------------------------------------*/
361
362/*
363 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
364 * boot EBC mapping only supports a maximum of 16MBytes
365 * (4.ff00.0000 - 4.ffff.ffff).
366 * To solve this problem, the FLASH has to get remapped to another
367 * EBC address which accepts bigger regions:
368 *
369 * 0xfc00.0000 -> 4.cc00.0000
370 *
371 * For this we have to remap the CS0 and re-relocate the envrironment,
372 * since the original FLASH location which was needed upon startup is
373 * now not correct anymore.
374 */
375
376/* Memory Bank 0 (NOR-FLASH) initialization */
377#define CFG_EBC_PB0AP 0x10055e00
378#define CFG_EBC_PB0CR (CFG_BOOT_BASE_ADDR | 0x9a000)
379
380/* Memory Bank 2 (CPLD) initialization */
381#define CFG_EBC_PB2AP 0x00804240
382#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
383
384/* Memory Bank 3 (NAND-FLASH) initialization */
385#define CFG_EBC_PB3AP 0x018003c0
386#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
387
388#define CFG_EBC_CFG 0xB8400000 /* EBC0_CFG */
389
390/*
391 * PPC4xx GPIO Configuration
392 */
393#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
394{ \
395/* GPIO Core 0 */ \
396{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
397{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
398{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
399{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
400{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
401{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
402{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
403{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
404{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
405{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
406{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
407{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
408{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
409{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
410{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
411{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
412{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
413{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
414{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
415{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
416{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
417{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
418{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
419{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
420{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
421{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
422{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
423{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
424{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
425{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
426{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
427{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
428}, \
429{ \
430/* GPIO Core 1 */ \
431{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
432{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
433{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
434{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
435{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
436{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
437{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
438{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
439{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
440{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
441{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
442{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
443{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
444{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
445{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
446{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
447{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
448{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
449{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
450{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
451{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
452{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
453{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
454{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
455{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
456{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
457{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
458{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
459{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
460{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
461{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
462{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
463} \
464}
465
466/* pass open firmware flat tree */
467#define CONFIG_OF_LIBFDT 1
468#define CONFIG_OF_BOARD_SETUP 1
469
470#endif /* __CONFIG_H */