| Yoshihiro Shimoda | ad1a3a9 | 2007-12-03 22:58:45 +0900 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> |
| 3 | * |
| 4 | * SH7720 Internal I/O register |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | */ |
| 21 | |
| 22 | #ifndef _ASM_CPU_SH7720_H_ |
| 23 | #define _ASM_CPU_SH7720_H_ |
| 24 | |
| 25 | #define CACHE_OC_NUM_WAYS 4 |
| 26 | #define CCR_CACHE_INIT 0x0000000B |
| 27 | |
| 28 | /* EXP */ |
| 29 | #define TRA 0xFFFFFFD0 |
| 30 | #define EXPEVT 0xFFFFFFD4 |
| 31 | #define INTEVT 0xFFFFFFD8 |
| 32 | |
| 33 | /* MMU */ |
| 34 | #define MMUCR 0xFFFFFFE0 |
| 35 | #define PTEH 0xFFFFFFF0 |
| 36 | #define PTEL 0xFFFFFFF4 |
| 37 | #define TTB 0xFFFFFFF8 |
| 38 | |
| 39 | /* CACHE */ |
| 40 | #define CCR 0xFFFFFFEC |
| 41 | |
| 42 | /* INTC */ |
| 43 | #define IPRF 0xA4080000 |
| 44 | #define IPRG 0xA4080002 |
| 45 | #define IPRH 0xA4080004 |
| 46 | #define IPRI 0xA4080006 |
| 47 | #define IPRJ 0xA4080008 |
| 48 | #define IRR5 0xA4080020 |
| 49 | #define IRR6 0xA4080022 |
| 50 | #define IRR7 0xA4080024 |
| 51 | #define IRR8 0xA4080026 |
| 52 | #define IRR9 0xA4080028 |
| 53 | #define IRR0 0xA4140004 |
| 54 | #define IRR1 0xA4140006 |
| 55 | #define IRR2 0xA4140008 |
| 56 | #define IRR3 0xA414000A |
| 57 | #define IRR4 0xA414000C |
| 58 | #define ICR1 0xA4140010 |
| 59 | #define ICR2 0xA4140012 |
| 60 | #define PINTER 0xA4140014 |
| 61 | #define IPRC 0xA4140016 |
| 62 | #define IPRD 0xA4140018 |
| 63 | #define IPRE 0xA414001A |
| 64 | #define ICR0 0xA414FEE0 |
| 65 | #define IPRA 0xA414FEE2 |
| 66 | #define IPRB 0xA414FEE4 |
| 67 | |
| 68 | /* BSC */ |
| 69 | #define BSC_BASE 0xA4FD0000 |
| 70 | #define CMNCR (BSC_BASE + 0x00) |
| 71 | #define CS0BCR (BSC_BASE + 0x04) |
| 72 | #define CS2BCR (BSC_BASE + 0x08) |
| 73 | #define CS3BCR (BSC_BASE + 0x0C) |
| 74 | #define CS4BCR (BSC_BASE + 0x10) |
| 75 | #define CS5ABCR (BSC_BASE + 0x14) |
| 76 | #define CS5BBCR (BSC_BASE + 0x18) |
| 77 | #define CS6ABCR (BSC_BASE + 0x1C) |
| 78 | #define CS6BBCR (BSC_BASE + 0x20) |
| 79 | #define CS0WCR (BSC_BASE + 0x24) |
| 80 | #define CS2WCR (BSC_BASE + 0x28) |
| 81 | #define CS3WCR (BSC_BASE + 0x2C) |
| 82 | #define CS4WCR (BSC_BASE + 0x30) |
| 83 | #define CS5AWCR (BSC_BASE + 0x34) |
| 84 | #define CS5BWCR (BSC_BASE + 0x38) |
| 85 | #define CS6AWCR (BSC_BASE + 0x3C) |
| 86 | #define CS6BWCR (BSC_BASE + 0x40) |
| 87 | #define SDCR (BSC_BASE + 0x44) |
| 88 | #define RTCSR (BSC_BASE + 0x48) |
| 89 | #define RTCNR (BSC_BASE + 0x4C) |
| 90 | #define RTCOR (BSC_BASE + 0x50) |
| 91 | #define SDMR2 (BSC_BASE + 0x4000) |
| 92 | #define SDMR3 (BSC_BASE + 0x5000) |
| 93 | |
| 94 | /* DMAC */ |
| 95 | |
| 96 | /* CPG */ |
| 97 | #define UCLKCR 0xA40A0008 |
| 98 | #define FRQCR 0xA415FF80 |
| 99 | |
| 100 | /* LOW POWER MODE */ |
| 101 | |
| 102 | /* TMU */ |
| 103 | #define TMU_BASE 0xA412FE90 |
| 104 | #define TSTR (TMU_BASE + 0x02) |
| 105 | #define TCOR0 (TMU_BASE + 0x04) |
| 106 | #define TCNT0 (TMU_BASE + 0x08) |
| 107 | #define TCR0 (TMU_BASE + 0x0C) |
| 108 | #define TCOR1 (TMU_BASE + 0x10) |
| 109 | #define TCNT1 (TMU_BASE + 0x14) |
| 110 | #define TCR1 (TMU_BASE + 0x18) |
| 111 | #define TCOR2 (TMU_BASE + 0x1C) |
| 112 | #define TCNT2 (TMU_BASE + 0x20) |
| 113 | #define TCR2 (TMU_BASE + 0x24) |
| 114 | |
| 115 | /* TPU */ |
| 116 | #define TPU_BASE 0xA4480000 |
| 117 | #define TPU_TSTR (TPU_BASE + 0x00) |
| 118 | #define TPU_TCR0 (TPU_BASE + 0x10) |
| 119 | #define TPU_TMDR0 (TPU_BASE + 0x14) |
| 120 | #define TPU_TIOR0 (TPU_BASE + 0x18) |
| 121 | #define TPU_TIER0 (TPU_BASE + 0x1C) |
| 122 | #define TPU_TSR0 (TPU_BASE + 0x20) |
| 123 | #define TPU_TCNT0 (TPU_BASE + 0x24) |
| 124 | #define TPU_TGRA0 (TPU_BASE + 0x28) |
| 125 | #define TPU_TGRB0 (TPU_BASE + 0x2C) |
| 126 | #define TPU_TGRC0 (TPU_BASE + 0x30) |
| 127 | #define TPU_TGRD0 (TPU_BASE + 0x34) |
| 128 | #define TPU_TCR1 (TPU_BASE + 0x50) |
| 129 | #define TPU_TMDR1 (TPU_BASE + 0x54) |
| 130 | #define TPU_TIOR1 (TPU_BASE + 0x58) |
| 131 | #define TPU_TIER1 (TPU_BASE + 0x5C) |
| 132 | #define TPU_TSR1 (TPU_BASE + 0x60) |
| 133 | #define TPU_TCNT1 (TPU_BASE + 0x64) |
| 134 | #define TPU_TGRA1 (TPU_BASE + 0x68) |
| 135 | #define TPU_TGRB1 (TPU_BASE + 0x6C) |
| 136 | #define TPU_TGRC1 (TPU_BASE + 0x70) |
| 137 | #define TPU_TGRD1 (TPU_BASE + 0x74) |
| 138 | #define TPU_TCR2 (TPU_BASE + 0x90) |
| 139 | #define TPU_TMDR2 (TPU_BASE + 0x94) |
| 140 | #define TPU_TIOR2 (TPU_BASE + 0x98) |
| 141 | #define TPU_TIER2 (TPU_BASE + 0x9C) |
| 142 | #define TPU_TSR2 (TPU_BASE + 0xB0) |
| 143 | #define TPU_TCNT2 (TPU_BASE + 0xB4) |
| 144 | #define TPU_TGRA2 (TPU_BASE + 0xB8) |
| 145 | #define TPU_TGRB2 (TPU_BASE + 0xBC) |
| 146 | #define TPU_TGRC2 (TPU_BASE + 0xC0) |
| 147 | #define TPU_TGRD2 (TPU_BASE + 0xC4) |
| 148 | #define TPU_TCR3 (TPU_BASE + 0xD0) |
| 149 | #define TPU_TMDR3 (TPU_BASE + 0xD4) |
| 150 | #define TPU_TIOR3 (TPU_BASE + 0xD8) |
| 151 | #define TPU_TIER3 (TPU_BASE + 0xDC) |
| 152 | #define TPU_TSR3 (TPU_BASE + 0xE0) |
| 153 | #define TPU_TCNT3 (TPU_BASE + 0xE4) |
| 154 | #define TPU_TGRA3 (TPU_BASE + 0xE8) |
| 155 | #define TPU_TGRB3 (TPU_BASE + 0xEC) |
| 156 | #define TPU_TGRC3 (TPU_BASE + 0xF0) |
| 157 | #define TPU_TGRD3 (TPU_BASE + 0xF4) |
| 158 | |
| 159 | /* CMT */ |
| 160 | |
| 161 | /* SIOF */ |
| 162 | |
| 163 | /* SCIF */ |
| 164 | #define SCIF0_BASE 0xA4430000 |
| 165 | |
| 166 | /* SIM */ |
| 167 | |
| 168 | /* IrDA */ |
| 169 | |
| 170 | /* IIC */ |
| 171 | |
| 172 | /* LCDC */ |
| 173 | |
| 174 | /* USBF */ |
| 175 | |
| 176 | /* MMCIF */ |
| 177 | |
| 178 | /* PFC */ |
| 179 | #define PFC_BASE 0xA4050100 |
| 180 | #define PACR (PFC_BASE + 0x00) |
| 181 | #define PBCR (PFC_BASE + 0x02) |
| 182 | #define PCCR (PFC_BASE + 0x04) |
| 183 | #define PDCR (PFC_BASE + 0x06) |
| 184 | #define PECR (PFC_BASE + 0x08) |
| 185 | #define PFCR (PFC_BASE + 0x0A) |
| 186 | #define PGCR (PFC_BASE + 0x0C) |
| 187 | #define PHCR (PFC_BASE + 0x0E) |
| 188 | #define PJCR (PFC_BASE + 0x10) |
| 189 | #define PKCR (PFC_BASE + 0x12) |
| 190 | #define PLCR (PFC_BASE + 0x14) |
| 191 | #define PMCR (PFC_BASE + 0x16) |
| 192 | #define PPCR (PFC_BASE + 0x18) |
| 193 | #define PRCR (PFC_BASE + 0x1A) |
| 194 | #define PSCR (PFC_BASE + 0x1C) |
| 195 | #define PTCR (PFC_BASE + 0x1E) |
| 196 | #define PUCR (PFC_BASE + 0x20) |
| 197 | #define PVCR (PFC_BASE + 0x22) |
| 198 | #define PSELA (PFC_BASE + 0x24) |
| 199 | #define PSELB (PFC_BASE + 0x26) |
| 200 | #define PSELC (PFC_BASE + 0x28) |
| 201 | #define PSELD (PFC_BASE + 0x2A) |
| 202 | |
| 203 | /* I/O Port */ |
| 204 | |
| 205 | /* H-UDI */ |
| 206 | |
| 207 | #endif /* _ASM_CPU_SH7720_H_ */ |