Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 1ea9789 | 2020-05-10 11:40:00 -0600 | [diff] [blame] | 7 | #include <bootstage.h> |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 8 | #include <dm.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 9 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 10 | #include <log.h> |
Philipp Tomsich | aad4d57 | 2017-09-11 22:04:16 +0200 | [diff] [blame] | 11 | #include <dm/ofnode.h> |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 12 | #include <mapmem.h> |
Kever Yang | 9fbe17c | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 13 | #include <asm/arch-rockchip/timer.h> |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 14 | #include <dt-structs.h> |
| 15 | #include <timer.h> |
| 16 | #include <asm/io.h> |
| 17 | |
| 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
| 20 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 21 | struct rockchip_timer_plat { |
| 22 | struct dtd_rockchip_rk3368_timer dtd; |
| 23 | }; |
| 24 | #endif |
| 25 | |
| 26 | /* Driver private data. Contains timer id. Could be either 0 or 1. */ |
| 27 | struct rockchip_timer_priv { |
| 28 | struct rk_timer *timer; |
| 29 | }; |
| 30 | |
Philipp Tomsich | aad4d57 | 2017-09-11 22:04:16 +0200 | [diff] [blame] | 31 | static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer) |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 32 | { |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 33 | uint64_t timebase_h, timebase_l; |
| 34 | uint64_t cntr; |
| 35 | |
Philipp Tomsich | aad4d57 | 2017-09-11 22:04:16 +0200 | [diff] [blame] | 36 | timebase_l = readl(&timer->timer_curr_value0); |
| 37 | timebase_h = readl(&timer->timer_curr_value1); |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 38 | |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 39 | cntr = timebase_h << 32 | timebase_l; |
Philipp Tomsich | aad4d57 | 2017-09-11 22:04:16 +0200 | [diff] [blame] | 40 | return cntr; |
| 41 | } |
| 42 | |
| 43 | #if CONFIG_IS_ENABLED(BOOTSTAGE) |
| 44 | ulong timer_get_boot_us(void) |
| 45 | { |
| 46 | uint64_t ticks = 0; |
| 47 | uint32_t rate; |
| 48 | uint64_t us; |
| 49 | int ret; |
| 50 | |
| 51 | ret = dm_timer_init(); |
| 52 | |
| 53 | if (!ret) { |
| 54 | /* The timer is available */ |
| 55 | rate = timer_get_rate(gd->timer); |
| 56 | timer_get_count(gd->timer, &ticks); |
| 57 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
| 58 | } else if (ret == -EAGAIN) { |
| 59 | /* We have been called so early that the DM is not ready,... */ |
| 60 | ofnode node = offset_to_ofnode(-1); |
| 61 | struct rk_timer *timer = NULL; |
| 62 | |
| 63 | /* |
| 64 | * ... so we try to access the raw timer, if it is specified |
| 65 | * via the tick-timer property in /chosen. |
| 66 | */ |
| 67 | node = ofnode_get_chosen_node("tick-timer"); |
| 68 | if (!ofnode_valid(node)) { |
| 69 | debug("%s: no /chosen/tick-timer\n", __func__); |
| 70 | return 0; |
| 71 | } |
| 72 | |
| 73 | timer = (struct rk_timer *)ofnode_get_addr(node); |
| 74 | |
| 75 | /* This timer is down-counting */ |
| 76 | ticks = ~0uLL - rockchip_timer_get_curr_value(timer); |
| 77 | if (ofnode_read_u32(node, "clock-frequency", &rate)) { |
| 78 | debug("%s: could not read clock-frequency\n", __func__); |
| 79 | return 0; |
| 80 | } |
| 81 | #endif |
| 82 | } else { |
| 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | us = (ticks * 1000) / rate; |
| 87 | return us; |
| 88 | } |
| 89 | #endif |
| 90 | |
| 91 | static int rockchip_timer_get_count(struct udevice *dev, u64 *count) |
| 92 | { |
| 93 | struct rockchip_timer_priv *priv = dev_get_priv(dev); |
| 94 | uint64_t cntr = rockchip_timer_get_curr_value(priv->timer); |
| 95 | |
| 96 | /* timers are down-counting */ |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 97 | *count = ~0ull - cntr; |
| 98 | return 0; |
| 99 | } |
| 100 | |
| 101 | static int rockchip_clk_ofdata_to_platdata(struct udevice *dev) |
| 102 | { |
| 103 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
| 104 | struct rockchip_timer_priv *priv = dev_get_priv(dev); |
| 105 | |
Philipp Tomsich | 41f2c21 | 2017-09-11 22:04:17 +0200 | [diff] [blame] | 106 | priv->timer = dev_read_addr_ptr(dev); |
| 107 | if (!priv->timer) |
| 108 | return -ENOENT; |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 109 | #endif |
| 110 | |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | static int rockchip_timer_start(struct udevice *dev) |
| 115 | { |
| 116 | struct rockchip_timer_priv *priv = dev_get_priv(dev); |
| 117 | const uint64_t reload_val = ~0uLL; |
| 118 | const uint32_t reload_val_l = reload_val & 0xffffffff; |
| 119 | const uint32_t reload_val_h = reload_val >> 32; |
| 120 | |
Philipp Tomsich | aad4d57 | 2017-09-11 22:04:16 +0200 | [diff] [blame] | 121 | /* don't reinit, if the timer is already running and set up */ |
| 122 | if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 && |
| 123 | (readl(&priv->timer->timer_load_count0) == reload_val_l) && |
| 124 | (readl(&priv->timer->timer_load_count1) == reload_val_h)) |
| 125 | return 0; |
| 126 | |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 127 | /* disable timer and reset all control */ |
| 128 | writel(0, &priv->timer->timer_ctrl_reg); |
| 129 | /* write reload value */ |
| 130 | writel(reload_val_l, &priv->timer->timer_load_count0); |
| 131 | writel(reload_val_h, &priv->timer->timer_load_count1); |
| 132 | /* enable timer */ |
| 133 | writel(1, &priv->timer->timer_ctrl_reg); |
| 134 | |
| 135 | return 0; |
| 136 | } |
| 137 | |
| 138 | static int rockchip_timer_probe(struct udevice *dev) |
| 139 | { |
| 140 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 141 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
| 142 | struct rockchip_timer_priv *priv = dev_get_priv(dev); |
| 143 | struct rockchip_timer_plat *plat = dev_get_platdata(dev); |
| 144 | |
Philipp Tomsich | 2924a36 | 2017-08-14 19:05:31 +0200 | [diff] [blame] | 145 | priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 146 | uc_priv->clock_rate = plat->dtd.clock_frequency; |
| 147 | #endif |
| 148 | |
| 149 | return rockchip_timer_start(dev); |
| 150 | } |
| 151 | |
| 152 | static const struct timer_ops rockchip_timer_ops = { |
| 153 | .get_count = rockchip_timer_get_count, |
| 154 | }; |
| 155 | |
| 156 | static const struct udevice_id rockchip_timer_ids[] = { |
Philipp Tomsich | 84e0114 | 2018-04-25 14:07:06 +0200 | [diff] [blame] | 157 | { .compatible = "rockchip,rk3188-timer" }, |
| 158 | { .compatible = "rockchip,rk3288-timer" }, |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 159 | { .compatible = "rockchip,rk3368-timer" }, |
| 160 | {} |
| 161 | }; |
| 162 | |
Philipp Tomsich | 9b32b57 | 2017-08-25 13:22:00 +0200 | [diff] [blame] | 163 | U_BOOT_DRIVER(rockchip_rk3368_timer) = { |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 164 | .name = "rockchip_rk3368_timer", |
| 165 | .id = UCLASS_TIMER, |
| 166 | .of_match = rockchip_timer_ids, |
| 167 | .probe = rockchip_timer_probe, |
| 168 | .ops = &rockchip_timer_ops, |
Philipp Tomsich | 02a61b7 | 2017-07-28 17:43:19 +0200 | [diff] [blame] | 169 | .priv_auto_alloc_size = sizeof(struct rockchip_timer_priv), |
| 170 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 171 | .platdata_auto_alloc_size = sizeof(struct rockchip_timer_plat), |
| 172 | #endif |
| 173 | .ofdata_to_platdata = rockchip_clk_ofdata_to_platdata, |
| 174 | }; |