Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / a9705f0348680c46abeaef14acd43878093818ed / . / dts / upstream / src / arm64 / qcom / msm8996.dtsi
blob: 1601e46549e77990dafbd63894b9c078ffec60af [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,gcc-msm8996.h>
8#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9#include <dt-bindings/clock/qcom,rpmcc.h>
10#include <dt-bindings/interconnect/qcom,msm8996.h>
11#include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12#include <dt-bindings/firmware/qcom,scm.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/power/qcom-rpmpd.h>
15#include <dt-bindings/soc/qcom,apr.h>
16#include <dt-bindings/thermal/thermal.h>
17
18/ {
19 interrupt-parent = <&intc>;
20
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 chosen { };
25
26 clocks {
27 xo_board: xo-board {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <19200000>;
31 clock-output-names = "xo_board";
32 };
33
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32764>;
38 clock-output-names = "sleep_clk";
39 };
40 };
41
42 cpus {
43 #address-cells = <2>;
44 #size-cells = <0>;
45
46 CPU0: cpu@0 {
47 device_type = "cpu";
48 compatible = "qcom,kryo";
49 reg = <0x0 0x0>;
50 enable-method = "psci";
51 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = <1024>;
53 clocks = <&kryocc 0>;
54 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
55 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>;
57 next-level-cache = <&L2_0>;
58 L2_0: l2-cache {
59 compatible = "cache";
60 cache-level = <2>;
61 cache-unified;
62 };
63 };
64
65 CPU1: cpu@1 {
66 device_type = "cpu";
67 compatible = "qcom,kryo";
68 reg = <0x0 0x1>;
69 enable-method = "psci";
70 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = <1024>;
72 clocks = <&kryocc 0>;
73 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
74 operating-points-v2 = <&cluster0_opp>;
75 #cooling-cells = <2>;
76 next-level-cache = <&L2_0>;
77 };
78
79 CPU2: cpu@100 {
80 device_type = "cpu";
81 compatible = "qcom,kryo";
82 reg = <0x0 0x100>;
83 enable-method = "psci";
84 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = <1024>;
86 clocks = <&kryocc 1>;
87 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
88 operating-points-v2 = <&cluster1_opp>;
89 #cooling-cells = <2>;
90 next-level-cache = <&L2_1>;
91 L2_1: l2-cache {
92 compatible = "cache";
93 cache-level = <2>;
94 cache-unified;
95 };
96 };
97
98 CPU3: cpu@101 {
99 device_type = "cpu";
100 compatible = "qcom,kryo";
101 reg = <0x0 0x101>;
102 enable-method = "psci";
103 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = <1024>;
105 clocks = <&kryocc 1>;
106 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
107 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>;
109 next-level-cache = <&L2_1>;
110 };
111
112 cpu-map {
113 cluster0 {
114 core0 {
115 cpu = <&CPU0>;
116 };
117
118 core1 {
119 cpu = <&CPU1>;
120 };
121 };
122
123 cluster1 {
124 core0 {
125 cpu = <&CPU2>;
126 };
127
128 core1 {
129 cpu = <&CPU3>;
130 };
131 };
132 };
133
134 idle-states {
135 entry-method = "psci";
136
137 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = "arm,idle-state";
139 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspend-param = <0x00000004>;
141 entry-latency-us = <130>;
142 exit-latency-us = <80>;
143 min-residency-us = <300>;
144 };
145 };
146 };
147
148 cluster0_opp: opp-table-cluster0 {
149 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse>;
151 opp-shared;
152
153 /* Nominal fmax for now */
154 opp-307200000 {
155 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0xf>;
157 clock-latency-ns = <200000>;
158 opp-peak-kBps = <307200>;
159 };
160 opp-422400000 {
161 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0xf>;
163 clock-latency-ns = <200000>;
164 opp-peak-kBps = <307200>;
165 };
166 opp-480000000 {
167 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0xf>;
169 clock-latency-ns = <200000>;
170 opp-peak-kBps = <307200>;
171 };
172 opp-556800000 {
173 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0xf>;
175 clock-latency-ns = <200000>;
176 opp-peak-kBps = <307200>;
177 };
178 opp-652800000 {
179 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0xf>;
181 clock-latency-ns = <200000>;
182 opp-peak-kBps = <384000>;
183 };
184 opp-729600000 {
185 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0xf>;
187 clock-latency-ns = <200000>;
188 opp-peak-kBps = <460800>;
189 };
190 opp-844800000 {
191 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0xf>;
193 clock-latency-ns = <200000>;
194 opp-peak-kBps = <537600>;
195 };
196 opp-960000000 {
197 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0xf>;
199 clock-latency-ns = <200000>;
200 opp-peak-kBps = <672000>;
201 };
202 opp-1036800000 {
203 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0xf>;
205 clock-latency-ns = <200000>;
206 opp-peak-kBps = <672000>;
207 };
208 opp-1113600000 {
209 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0xf>;
211 clock-latency-ns = <200000>;
212 opp-peak-kBps = <825600>;
213 };
214 opp-1190400000 {
215 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0xf>;
217 clock-latency-ns = <200000>;
218 opp-peak-kBps = <825600>;
219 };
220 opp-1228800000 {
221 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0xf>;
223 clock-latency-ns = <200000>;
224 opp-peak-kBps = <902400>;
225 };
226 opp-1324800000 {
227 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0xd>;
229 clock-latency-ns = <200000>;
230 opp-peak-kBps = <1056000>;
231 };
232 opp-1363200000 {
233 opp-hz = /bits/ 64 <1363200000>;
234 opp-supported-hw = <0x2>;
235 clock-latency-ns = <200000>;
236 opp-peak-kBps = <1132800>;
237 };
238 opp-1401600000 {
239 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0xd>;
241 clock-latency-ns = <200000>;
242 opp-peak-kBps = <1132800>;
243 };
244 opp-1478400000 {
245 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x9>;
247 clock-latency-ns = <200000>;
248 opp-peak-kBps = <1190400>;
249 };
250 opp-1497600000 {
251 opp-hz = /bits/ 64 <1497600000>;
252 opp-supported-hw = <0x04>;
253 clock-latency-ns = <200000>;
254 opp-peak-kBps = <1305600>;
255 };
256 opp-1593600000 {
257 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x9>;
259 clock-latency-ns = <200000>;
260 opp-peak-kBps = <1382400>;
261 };
262 };
263
264 cluster1_opp: opp-table-cluster1 {
265 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse>;
267 opp-shared;
268
269 /* Nominal fmax for now */
270 opp-307200000 {
271 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0xf>;
273 clock-latency-ns = <200000>;
274 opp-peak-kBps = <307200>;
275 };
276 opp-403200000 {
277 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0xf>;
279 clock-latency-ns = <200000>;
280 opp-peak-kBps = <307200>;
281 };
282 opp-480000000 {
283 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0xf>;
285 clock-latency-ns = <200000>;
286 opp-peak-kBps = <307200>;
287 };
288 opp-556800000 {
289 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0xf>;
291 clock-latency-ns = <200000>;
292 opp-peak-kBps = <307200>;
293 };
294 opp-652800000 {
295 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0xf>;
297 clock-latency-ns = <200000>;
298 opp-peak-kBps = <307200>;
299 };
300 opp-729600000 {
301 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0xf>;
303 clock-latency-ns = <200000>;
304 opp-peak-kBps = <307200>;
305 };
306 opp-806400000 {
307 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0xf>;
309 clock-latency-ns = <200000>;
310 opp-peak-kBps = <384000>;
311 };
312 opp-883200000 {
313 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0xf>;
315 clock-latency-ns = <200000>;
316 opp-peak-kBps = <460800>;
317 };
318 opp-940800000 {
319 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0xf>;
321 clock-latency-ns = <200000>;
322 opp-peak-kBps = <537600>;
323 };
324 opp-1036800000 {
325 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0xf>;
327 clock-latency-ns = <200000>;
328 opp-peak-kBps = <595200>;
329 };
330 opp-1113600000 {
331 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0xf>;
333 clock-latency-ns = <200000>;
334 opp-peak-kBps = <672000>;
335 };
336 opp-1190400000 {
337 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0xf>;
339 clock-latency-ns = <200000>;
340 opp-peak-kBps = <672000>;
341 };
342 opp-1248000000 {
343 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0xf>;
345 clock-latency-ns = <200000>;
346 opp-peak-kBps = <748800>;
347 };
348 opp-1324800000 {
349 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0xf>;
351 clock-latency-ns = <200000>;
352 opp-peak-kBps = <825600>;
353 };
354 opp-1401600000 {
355 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0xf>;
357 clock-latency-ns = <200000>;
358 opp-peak-kBps = <902400>;
359 };
360 opp-1478400000 {
361 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0xf>;
363 clock-latency-ns = <200000>;
364 opp-peak-kBps = <979200>;
365 };
366 opp-1555200000 {
367 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0xf>;
369 clock-latency-ns = <200000>;
370 opp-peak-kBps = <1056000>;
371 };
372 opp-1632000000 {
373 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0xf>;
375 clock-latency-ns = <200000>;
376 opp-peak-kBps = <1190400>;
377 };
378 opp-1708800000 {
379 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0xf>;
381 clock-latency-ns = <200000>;
382 opp-peak-kBps = <1228800>;
383 };
384 opp-1785600000 {
385 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0xf>;
387 clock-latency-ns = <200000>;
388 opp-peak-kBps = <1305600>;
389 };
390 opp-1804800000 {
391 opp-hz = /bits/ 64 <1804800000>;
392 opp-supported-hw = <0xe>;
393 clock-latency-ns = <200000>;
394 opp-peak-kBps = <1305600>;
395 };
396 opp-1824000000 {
397 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x1>;
399 clock-latency-ns = <200000>;
400 opp-peak-kBps = <1382400>;
401 };
402 opp-1900800000 {
403 opp-hz = /bits/ 64 <1900800000>;
404 opp-supported-hw = <0x4>;
405 clock-latency-ns = <200000>;
406 opp-peak-kBps = <1305600>;
407 };
408 opp-1920000000 {
409 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x1>;
411 clock-latency-ns = <200000>;
412 opp-peak-kBps = <1459200>;
413 };
414 opp-1996800000 {
415 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x1>;
417 clock-latency-ns = <200000>;
418 opp-peak-kBps = <1593600>;
419 };
420 opp-2073600000 {
421 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x1>;
423 clock-latency-ns = <200000>;
424 opp-peak-kBps = <1593600>;
425 };
426 opp-2150400000 {
427 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x1>;
429 clock-latency-ns = <200000>;
430 opp-peak-kBps = <1593600>;
431 };
432 };
433
434 firmware {
435 scm {
436 compatible = "qcom,scm-msm8996", "qcom,scm";
437 qcom,dload-mode = <&tcsr_2 0x13000>;
438 };
439 };
440
441 memory@80000000 {
442 device_type = "memory";
443 /* We expect the bootloader to fill in the reg */
444 reg = <0x0 0x80000000 0x0 0x0>;
445 };
446
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]447 etm {
448 compatible = "qcom,coresight-remote-etm";
449
450 out-ports {
451 port {
452 modem_etm_out_funnel_in2: endpoint {
453 remote-endpoint =
454 <&funnel_in2_in_modem_etm>;
455 };
456 };
457 };
458 };
459
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]460 psci {
461 compatible = "arm,psci-1.0";
462 method = "smc";
463 };
464
465 rpm: remoteproc {
466 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
467
468 glink-edge {
469 compatible = "qcom,glink-rpm";
470 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
471 qcom,rpm-msg-ram = <&rpm_msg_ram>;
472 mboxes = <&apcs_glb 0>;
473
474 rpm_requests: rpm-requests {
475 compatible = "qcom,rpm-msm8996";
476 qcom,glink-channels = "rpm_requests";
477
478 rpmcc: clock-controller {
479 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
480 #clock-cells = <1>;
481 clocks = <&xo_board>;
482 clock-names = "xo";
483 };
484
485 rpmpd: power-controller {
486 compatible = "qcom,msm8996-rpmpd";
487 #power-domain-cells = <1>;
488 operating-points-v2 = <&rpmpd_opp_table>;
489
490 rpmpd_opp_table: opp-table {
491 compatible = "operating-points-v2";
492
493 rpmpd_opp1: opp1 {
494 opp-level = <1>;
495 };
496
497 rpmpd_opp2: opp2 {
498 opp-level = <2>;
499 };
500
501 rpmpd_opp3: opp3 {
502 opp-level = <3>;
503 };
504
505 rpmpd_opp4: opp4 {
506 opp-level = <4>;
507 };
508
509 rpmpd_opp5: opp5 {
510 opp-level = <5>;
511 };
512
513 rpmpd_opp6: opp6 {
514 opp-level = <6>;
515 };
516 };
517 };
518 };
519 };
520 };
521
522 reserved-memory {
523 #address-cells = <2>;
524 #size-cells = <2>;
525 ranges;
526
527 hyp_mem: memory@85800000 {
528 reg = <0x0 0x85800000 0x0 0x600000>;
529 no-map;
530 };
531
532 xbl_mem: memory@85e00000 {
533 reg = <0x0 0x85e00000 0x0 0x200000>;
534 no-map;
535 };
536
537 smem_mem: smem-mem@86000000 {
538 reg = <0x0 0x86000000 0x0 0x200000>;
539 no-map;
540 };
541
542 tz_mem: memory@86200000 {
543 reg = <0x0 0x86200000 0x0 0x2600000>;
544 no-map;
545 };
546
547 rmtfs_mem: rmtfs {
548 compatible = "qcom,rmtfs-mem";
549
550 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
552 no-map;
553
554 qcom,client-id = <1>;
555 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
556 };
557
558 mpss_mem: mpss@88800000 {
559 reg = <0x0 0x88800000 0x0 0x6200000>;
560 no-map;
561 };
562
563 adsp_mem: adsp@8ea00000 {
564 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
565 no-map;
566 };
567
568 slpi_mem: slpi@90500000 {
569 reg = <0x0 0x90500000 0x0 0xa00000>;
570 no-map;
571 };
572
573 gpu_mem: gpu@90f00000 {
574 compatible = "shared-dma-pool";
575 reg = <0x0 0x90f00000 0x0 0x100000>;
576 no-map;
577 };
578
579 venus_mem: venus@91000000 {
580 reg = <0x0 0x91000000 0x0 0x500000>;
581 no-map;
582 };
583
584 mba_mem: mba@91500000 {
585 reg = <0x0 0x91500000 0x0 0x200000>;
586 no-map;
587 };
588
589 mdata_mem: mpss-metadata {
590 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
591 size = <0x0 0x4000>;
592 no-map;
593 };
594 };
595
596 smem {
597 compatible = "qcom,smem";
598 memory-region = <&smem_mem>;
599 hwlocks = <&tcsr_mutex 3>;
600 };
601
602 smp2p-adsp {
603 compatible = "qcom,smp2p";
604 qcom,smem = <443>, <429>;
605
606 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
607
608 mboxes = <&apcs_glb 10>;
609
610 qcom,local-pid = <0>;
611 qcom,remote-pid = <2>;
612
613 adsp_smp2p_out: master-kernel {
614 qcom,entry-name = "master-kernel";
615 #qcom,smem-state-cells = <1>;
616 };
617
618 adsp_smp2p_in: slave-kernel {
619 qcom,entry-name = "slave-kernel";
620
621 interrupt-controller;
622 #interrupt-cells = <2>;
623 };
624 };
625
626 smp2p-mpss {
627 compatible = "qcom,smp2p";
628 qcom,smem = <435>, <428>;
629
630 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
631
632 mboxes = <&apcs_glb 14>;
633
634 qcom,local-pid = <0>;
635 qcom,remote-pid = <1>;
636
637 mpss_smp2p_out: master-kernel {
638 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells = <1>;
640 };
641
642 mpss_smp2p_in: slave-kernel {
643 qcom,entry-name = "slave-kernel";
644
645 interrupt-controller;
646 #interrupt-cells = <2>;
647 };
648 };
649
650 smp2p-slpi {
651 compatible = "qcom,smp2p";
652 qcom,smem = <481>, <430>;
653
654 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
655
656 mboxes = <&apcs_glb 26>;
657
658 qcom,local-pid = <0>;
659 qcom,remote-pid = <3>;
660
661 slpi_smp2p_out: master-kernel {
662 qcom,entry-name = "master-kernel";
663 #qcom,smem-state-cells = <1>;
664 };
665
666 slpi_smp2p_in: slave-kernel {
667 qcom,entry-name = "slave-kernel";
668
669 interrupt-controller;
670 #interrupt-cells = <2>;
671 };
672 };
673
674 soc: soc@0 {
675 #address-cells = <1>;
676 #size-cells = <1>;
677 ranges = <0 0 0 0xffffffff>;
678 compatible = "simple-bus";
679
680 pcie_phy: phy-wrapper@34000 {
681 compatible = "qcom,msm8996-qmp-pcie-phy";
682 reg = <0x00034000 0x488>;
683 #address-cells = <1>;
684 #size-cells = <1>;
685 ranges = <0x0 0x00034000 0x4000>;
686
687 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
688 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
689 <&gcc GCC_PCIE_CLKREF_CLK>;
690 clock-names = "aux", "cfg_ahb", "ref";
691
692 resets = <&gcc GCC_PCIE_PHY_BCR>,
693 <&gcc GCC_PCIE_PHY_COM_BCR>,
694 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
695 reset-names = "phy", "common", "cfg";
696
697 status = "disabled";
698
699 pciephy_0: phy@1000 {
700 reg = <0x1000 0x130>,
701 <0x1200 0x200>,
702 <0x1400 0x1dc>;
703
704 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
705 clock-names = "pipe0";
706 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
707 reset-names = "lane0";
708
709 #clock-cells = <0>;
710 clock-output-names = "pcie_0_pipe_clk_src";
711
712 #phy-cells = <0>;
713 };
714
715 pciephy_1: phy@2000 {
716 reg = <0x2000 0x130>,
717 <0x2200 0x200>,
718 <0x2400 0x1dc>;
719
720 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
721 clock-names = "pipe1";
722 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
723 reset-names = "lane1";
724
725 #clock-cells = <0>;
726 clock-output-names = "pcie_1_pipe_clk_src";
727
728 #phy-cells = <0>;
729 };
730
731 pciephy_2: phy@3000 {
732 reg = <0x3000 0x130>,
733 <0x3200 0x200>,
734 <0x3400 0x1dc>;
735
736 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
737 clock-names = "pipe2";
738 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
739 reset-names = "lane2";
740
741 #clock-cells = <0>;
742 clock-output-names = "pcie_2_pipe_clk_src";
743
744 #phy-cells = <0>;
745 };
746 };
747
748 rpm_msg_ram: sram@68000 {
749 compatible = "qcom,rpm-msg-ram";
750 reg = <0x00068000 0x6000>;
751 };
752
753 qfprom@74000 {
754 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
755 reg = <0x00074000 0x8ff>;
756 #address-cells = <1>;
757 #size-cells = <1>;
758
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]759 qusb2p_hstx_trim: hstx-trim@24e {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]760 reg = <0x24e 0x2>;
761 bits = <5 4>;
762 };
763
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]764 qusb2s_hstx_trim: hstx-trim@24f {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]765 reg = <0x24f 0x1>;
766 bits = <1 4>;
767 };
768
769 speedbin_efuse: speedbin@133 {
770 reg = <0x133 0x1>;
771 bits = <5 3>;
772 };
773 };
774
775 rng: rng@83000 {
776 compatible = "qcom,prng-ee";
777 reg = <0x00083000 0x1000>;
778 clocks = <&gcc GCC_PRNG_AHB_CLK>;
779 clock-names = "core";
780 };
781
782 gcc: clock-controller@300000 {
783 compatible = "qcom,gcc-msm8996";
784 #clock-cells = <1>;
785 #reset-cells = <1>;
786 #power-domain-cells = <1>;
787 reg = <0x00300000 0x90000>;
788
789 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
790 <&rpmcc RPM_SMD_LN_BB_CLK>,
791 <&sleep_clk>,
792 <&pciephy_0>,
793 <&pciephy_1>,
794 <&pciephy_2>,
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]795 <&usb3phy>,
796 <&ufsphy 0>,
797 <&ufsphy 1>,
798 <&ufsphy 2>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]799 clock-names = "cxo",
800 "cxo2",
801 "sleep_clk",
802 "pcie_0_pipe_clk_src",
803 "pcie_1_pipe_clk_src",
804 "pcie_2_pipe_clk_src",
805 "usb3_phy_pipe_clk_src",
806 "ufs_rx_symbol_0_clk_src",
807 "ufs_rx_symbol_1_clk_src",
808 "ufs_tx_symbol_0_clk_src";
809 };
810
811 bimc: interconnect@408000 {
812 compatible = "qcom,msm8996-bimc";
813 reg = <0x00408000 0x5a000>;
814 #interconnect-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]815 };
816
817 tsens0: thermal-sensor@4a9000 {
818 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
819 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x1000>; /* SROT */
821 #qcom,sensors = <13>;
822 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
824 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells = <1>;
826 };
827
828 tsens1: thermal-sensor@4ad000 {
829 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
830 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x1000>; /* SROT */
832 #qcom,sensors = <8>;
833 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "uplow", "critical";
836 #thermal-sensor-cells = <1>;
837 };
838
839 cryptobam: dma-controller@644000 {
840 compatible = "qcom,bam-v1.7.0";
841 reg = <0x00644000 0x24000>;
842 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&gcc GCC_CE1_CLK>;
844 clock-names = "bam_clk";
845 #dma-cells = <1>;
846 qcom,ee = <0>;
847 qcom,controlled-remotely;
848 };
849
850 crypto: crypto@67a000 {
851 compatible = "qcom,crypto-v5.4";
852 reg = <0x0067a000 0x6000>;
853 clocks = <&gcc GCC_CE1_AHB_CLK>,
854 <&gcc GCC_CE1_AXI_CLK>,
855 <&gcc GCC_CE1_CLK>;
856 clock-names = "iface", "bus", "core";
857 dmas = <&cryptobam 6>, <&cryptobam 7>;
858 dma-names = "rx", "tx";
859 };
860
861 cnoc: interconnect@500000 {
862 compatible = "qcom,msm8996-cnoc";
863 reg = <0x00500000 0x1000>;
864 #interconnect-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]865 };
866
867 snoc: interconnect@524000 {
868 compatible = "qcom,msm8996-snoc";
869 reg = <0x00524000 0x1c000>;
870 #interconnect-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]871 };
872
873 a0noc: interconnect@543000 {
874 compatible = "qcom,msm8996-a0noc";
875 reg = <0x00543000 0x6000>;
876 #interconnect-cells = <1>;
877 clock-names = "aggre0_snoc_axi",
878 "aggre0_cnoc_ahb",
879 "aggre0_noc_mpu_cfg";
880 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
881 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
882 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
883 power-domains = <&gcc AGGRE0_NOC_GDSC>;
884 };
885
886 a1noc: interconnect@562000 {
887 compatible = "qcom,msm8996-a1noc";
888 reg = <0x00562000 0x5000>;
889 #interconnect-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]890 };
891
892 a2noc: interconnect@583000 {
893 compatible = "qcom,msm8996-a2noc";
894 reg = <0x00583000 0x7000>;
895 #interconnect-cells = <1>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]896 clock-names = "aggre2_ufs_axi", "ufs_axi";
897 clocks = <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]898 <&gcc GCC_UFS_AXI_CLK>;
899 };
900
901 mnoc: interconnect@5a4000 {
902 compatible = "qcom,msm8996-mnoc";
903 reg = <0x005a4000 0x1c000>;
904 #interconnect-cells = <1>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]905 clock-names = "iface";
906 clocks = <&mmcc AHB_CLK_SRC>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]907 };
908
909 pnoc: interconnect@5c0000 {
910 compatible = "qcom,msm8996-pnoc";
911 reg = <0x005c0000 0x3000>;
912 #interconnect-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]913 };
914
915 tcsr_mutex: hwlock@740000 {
916 compatible = "qcom,tcsr-mutex";
917 reg = <0x00740000 0x20000>;
918 #hwlock-cells = <1>;
919 };
920
921 tcsr_1: syscon@760000 {
922 compatible = "qcom,tcsr-msm8996", "syscon";
923 reg = <0x00760000 0x20000>;
924 };
925
926 tcsr_2: syscon@7a0000 {
927 compatible = "qcom,tcsr-msm8996", "syscon";
928 reg = <0x007a0000 0x18000>;
929 };
930
931 mmcc: clock-controller@8c0000 {
932 compatible = "qcom,mmcc-msm8996";
933 #clock-cells = <1>;
934 #reset-cells = <1>;
935 #power-domain-cells = <1>;
936 reg = <0x008c0000 0x40000>;
937 clocks = <&xo_board>,
938 <&gcc GPLL0>,
939 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
940 <&mdss_dsi0_phy 1>,
941 <&mdss_dsi0_phy 0>,
942 <&mdss_dsi1_phy 1>,
943 <&mdss_dsi1_phy 0>,
944 <&mdss_hdmi_phy>;
945 clock-names = "xo",
946 "gpll0",
947 "gcc_mmss_noc_cfg_ahb_clk",
948 "dsi0pll",
949 "dsi0pllbyte",
950 "dsi1pll",
951 "dsi1pllbyte",
952 "hdmipll";
953 assigned-clocks = <&mmcc MMPLL9_PLL>,
954 <&mmcc MMPLL1_PLL>,
955 <&mmcc MMPLL3_PLL>,
956 <&mmcc MMPLL4_PLL>,
957 <&mmcc MMPLL5_PLL>;
958 assigned-clock-rates = <624000000>,
959 <810000000>,
960 <980000000>,
961 <960000000>,
962 <825000000>;
963 };
964
965 mdss: display-subsystem@900000 {
966 compatible = "qcom,mdss";
967
968 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x1040>,
970 <0x009b8000 0x1040>;
971 reg-names = "mdss_phys",
972 "vbif_phys",
973 "vbif_nrt_phys";
974
975 power-domains = <&mmcc MDSS_GDSC>;
976 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
977
978 interrupt-controller;
979 #interrupt-cells = <1>;
980
981 clocks = <&mmcc MDSS_AHB_CLK>,
982 <&mmcc MDSS_MDP_CLK>;
983 clock-names = "iface", "core";
984
985 #address-cells = <1>;
986 #size-cells = <1>;
987 ranges;
988
989 status = "disabled";
990
991 mdp: display-controller@901000 {
992 compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
993 reg = <0x00901000 0x90000>;
994 reg-names = "mdp_phys";
995
996 interrupt-parent = <&mdss>;
997 interrupts = <0>;
998
999 clocks = <&mmcc MDSS_AHB_CLK>,
1000 <&mmcc MDSS_AXI_CLK>,
1001 <&mmcc MDSS_MDP_CLK>,
1002 <&mmcc SMMU_MDP_AXI_CLK>,
1003 <&mmcc MDSS_VSYNC_CLK>;
1004 clock-names = "iface",
1005 "bus",
1006 "core",
1007 "iommu",
1008 "vsync";
1009
1010 iommus = <&mdp_smmu 0>;
1011
1012 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1013 <&mmcc MDSS_VSYNC_CLK>;
1014 assigned-clock-rates = <300000000>,
1015 <19200000>;
1016
1017 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1018 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
1019 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
1020 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1021
1022 ports {
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1025
1026 port@0 {
1027 reg = <0>;
1028 mdp5_intf3_out: endpoint {
1029 remote-endpoint = <&mdss_hdmi_in>;
1030 };
1031 };
1032
1033 port@1 {
1034 reg = <1>;
1035 mdp5_intf1_out: endpoint {
1036 remote-endpoint = <&mdss_dsi0_in>;
1037 };
1038 };
1039
1040 port@2 {
1041 reg = <2>;
1042 mdp5_intf2_out: endpoint {
1043 remote-endpoint = <&mdss_dsi1_in>;
1044 };
1045 };
1046 };
1047 };
1048
1049 mdss_dsi0: dsi@994000 {
1050 compatible = "qcom,msm8996-dsi-ctrl",
1051 "qcom,mdss-dsi-ctrl";
1052 reg = <0x00994000 0x400>;
1053 reg-names = "dsi_ctrl";
1054
1055 interrupt-parent = <&mdss>;
1056 interrupts = <4>;
1057
1058 clocks = <&mmcc MDSS_MDP_CLK>,
1059 <&mmcc MDSS_BYTE0_CLK>,
1060 <&mmcc MDSS_AHB_CLK>,
1061 <&mmcc MDSS_AXI_CLK>,
1062 <&mmcc MMSS_MISC_AHB_CLK>,
1063 <&mmcc MDSS_PCLK0_CLK>,
1064 <&mmcc MDSS_ESC0_CLK>;
1065 clock-names = "mdp_core",
1066 "byte",
1067 "iface",
1068 "bus",
1069 "core_mmss",
1070 "pixel",
1071 "core";
1072 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1073 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1074
1075 phys = <&mdss_dsi0_phy>;
1076 status = "disabled";
1077
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1080
1081 ports {
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1084
1085 port@0 {
1086 reg = <0>;
1087 mdss_dsi0_in: endpoint {
1088 remote-endpoint = <&mdp5_intf1_out>;
1089 };
1090 };
1091
1092 port@1 {
1093 reg = <1>;
1094 mdss_dsi0_out: endpoint {
1095 };
1096 };
1097 };
1098 };
1099
1100 mdss_dsi0_phy: phy@994400 {
1101 compatible = "qcom,dsi-phy-14nm";
1102 reg = <0x00994400 0x100>,
1103 <0x00994500 0x300>,
1104 <0x00994800 0x188>;
1105 reg-names = "dsi_phy",
1106 "dsi_phy_lane",
1107 "dsi_pll";
1108
1109 #clock-cells = <1>;
1110 #phy-cells = <0>;
1111
1112 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1113 clock-names = "iface", "ref";
1114 status = "disabled";
1115 };
1116
1117 mdss_dsi1: dsi@996000 {
1118 compatible = "qcom,msm8996-dsi-ctrl",
1119 "qcom,mdss-dsi-ctrl";
1120 reg = <0x00996000 0x400>;
1121 reg-names = "dsi_ctrl";
1122
1123 interrupt-parent = <&mdss>;
1124 interrupts = <5>;
1125
1126 clocks = <&mmcc MDSS_MDP_CLK>,
1127 <&mmcc MDSS_BYTE1_CLK>,
1128 <&mmcc MDSS_AHB_CLK>,
1129 <&mmcc MDSS_AXI_CLK>,
1130 <&mmcc MMSS_MISC_AHB_CLK>,
1131 <&mmcc MDSS_PCLK1_CLK>,
1132 <&mmcc MDSS_ESC1_CLK>;
1133 clock-names = "mdp_core",
1134 "byte",
1135 "iface",
1136 "bus",
1137 "core_mmss",
1138 "pixel",
1139 "core";
1140 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1141 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1142
1143 phys = <&mdss_dsi1_phy>;
1144 status = "disabled";
1145
1146 #address-cells = <1>;
1147 #size-cells = <0>;
1148
1149 ports {
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1152
1153 port@0 {
1154 reg = <0>;
1155 mdss_dsi1_in: endpoint {
1156 remote-endpoint = <&mdp5_intf2_out>;
1157 };
1158 };
1159
1160 port@1 {
1161 reg = <1>;
1162 mdss_dsi1_out: endpoint {
1163 };
1164 };
1165 };
1166 };
1167
1168 mdss_dsi1_phy: phy@996400 {
1169 compatible = "qcom,dsi-phy-14nm";
1170 reg = <0x00996400 0x100>,
1171 <0x00996500 0x300>,
1172 <0x00996800 0x188>;
1173 reg-names = "dsi_phy",
1174 "dsi_phy_lane",
1175 "dsi_pll";
1176
1177 #clock-cells = <1>;
1178 #phy-cells = <0>;
1179
1180 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1181 clock-names = "iface", "ref";
1182 status = "disabled";
1183 };
1184
1185 mdss_hdmi: hdmi-tx@9a0000 {
1186 compatible = "qcom,hdmi-tx-8996";
1187 reg = <0x009a0000 0x50c>,
1188 <0x00070000 0x6158>,
1189 <0x009e0000 0xfff>;
1190 reg-names = "core_physical",
1191 "qfprom_physical",
1192 "hdcp_physical";
1193
1194 interrupt-parent = <&mdss>;
1195 interrupts = <8>;
1196
1197 clocks = <&mmcc MDSS_MDP_CLK>,
1198 <&mmcc MDSS_AHB_CLK>,
1199 <&mmcc MDSS_HDMI_CLK>,
1200 <&mmcc MDSS_HDMI_AHB_CLK>,
1201 <&mmcc MDSS_EXTPCLK_CLK>;
1202 clock-names =
1203 "mdp_core",
1204 "iface",
1205 "core",
1206 "alt_iface",
1207 "extp";
1208
1209 phys = <&mdss_hdmi_phy>;
1210 #sound-dai-cells = <1>;
1211
1212 status = "disabled";
1213
1214 ports {
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1217
1218 port@0 {
1219 reg = <0>;
1220 mdss_hdmi_in: endpoint {
1221 remote-endpoint = <&mdp5_intf3_out>;
1222 };
1223 };
1224 };
1225 };
1226
1227 mdss_hdmi_phy: phy@9a0600 {
1228 #phy-cells = <0>;
1229 compatible = "qcom,hdmi-phy-8996";
1230 reg = <0x009a0600 0x1c4>,
1231 <0x009a0a00 0x124>,
1232 <0x009a0c00 0x124>,
1233 <0x009a0e00 0x124>,
1234 <0x009a1000 0x124>,
1235 <0x009a1200 0x0c8>;
1236 reg-names = "hdmi_pll",
1237 "hdmi_tx_l0",
1238 "hdmi_tx_l1",
1239 "hdmi_tx_l2",
1240 "hdmi_tx_l3",
1241 "hdmi_phy";
1242
1243 clocks = <&mmcc MDSS_AHB_CLK>,
1244 <&gcc GCC_HDMI_CLKREF_CLK>,
1245 <&xo_board>;
1246 clock-names = "iface",
1247 "ref",
1248 "xo";
1249
1250 #clock-cells = <0>;
1251
1252 status = "disabled";
1253 };
1254 };
1255
1256 gpu: gpu@b00000 {
1257 compatible = "qcom,adreno-530.2", "qcom,adreno";
1258
1259 reg = <0x00b00000 0x3f000>;
1260 reg-names = "kgsl_3d0_reg_memory";
1261
1262 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1263
1264 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1265 <&mmcc GPU_AHB_CLK>,
1266 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1267 <&gcc GCC_BIMC_GFX_CLK>,
1268 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1269
1270 clock-names = "core",
1271 "iface",
1272 "rbbmtimer",
1273 "mem",
1274 "mem_iface";
1275
1276 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
1277 interconnect-names = "gfx-mem";
1278
1279 power-domains = <&mmcc GPU_GX_GDSC>;
1280 iommus = <&adreno_smmu 0>;
1281
1282 nvmem-cells = <&speedbin_efuse>;
1283 nvmem-cell-names = "speed_bin";
1284
1285 operating-points-v2 = <&gpu_opp_table>;
1286
1287 status = "disabled";
1288
1289 #cooling-cells = <2>;
1290
1291 gpu_opp_table: opp-table {
1292 compatible = "operating-points-v2";
1293
1294 /*
1295 * 624Mhz is only available on speed bins 0 and 3.
1296 * 560Mhz is only available on speed bins 0, 2 and 3.
1297 * All the rest are available on all bins of the hardware.
1298 */
1299 opp-624000000 {
1300 opp-hz = /bits/ 64 <624000000>;
1301 opp-supported-hw = <0x09>;
1302 };
1303 opp-560000000 {
1304 opp-hz = /bits/ 64 <560000000>;
1305 opp-supported-hw = <0x0d>;
1306 };
1307 opp-510000000 {
1308 opp-hz = /bits/ 64 <510000000>;
1309 opp-supported-hw = <0xff>;
1310 };
1311 opp-401800000 {
1312 opp-hz = /bits/ 64 <401800000>;
1313 opp-supported-hw = <0xff>;
1314 };
1315 opp-315000000 {
1316 opp-hz = /bits/ 64 <315000000>;
1317 opp-supported-hw = <0xff>;
1318 };
1319 opp-214000000 {
1320 opp-hz = /bits/ 64 <214000000>;
1321 opp-supported-hw = <0xff>;
1322 };
1323 opp-133000000 {
1324 opp-hz = /bits/ 64 <133000000>;
1325 opp-supported-hw = <0xff>;
1326 };
1327 };
1328
1329 zap-shader {
1330 memory-region = <&gpu_mem>;
1331 };
1332 };
1333
1334 tlmm: pinctrl@1010000 {
1335 compatible = "qcom,msm8996-pinctrl";
1336 reg = <0x01010000 0x300000>;
1337 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1338 gpio-controller;
1339 gpio-ranges = <&tlmm 0 0 150>;
1340 #gpio-cells = <2>;
1341 interrupt-controller;
1342 #interrupt-cells = <2>;
1343
1344 blsp1_spi1_default: blsp1-spi1-default-state {
1345 spi-pins {
1346 pins = "gpio0", "gpio1", "gpio3";
1347 function = "blsp_spi1";
1348 drive-strength = <12>;
1349 bias-disable;
1350 };
1351
1352 cs-pins {
1353 pins = "gpio2";
1354 function = "gpio";
1355 drive-strength = <16>;
1356 bias-disable;
1357 output-high;
1358 };
1359 };
1360
1361 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1362 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1363 function = "gpio";
1364 drive-strength = <2>;
1365 bias-pull-down;
1366 };
1367
1368 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1369 pins = "gpio4", "gpio5";
1370 function = "blsp_uart8";
1371 drive-strength = <16>;
1372 bias-disable;
1373 };
1374
1375 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1376 pins = "gpio4", "gpio5";
1377 function = "gpio";
1378 drive-strength = <2>;
1379 bias-disable;
1380 };
1381
1382 blsp2_i2c2_default: blsp2-i2c2-state {
1383 pins = "gpio6", "gpio7";
1384 function = "blsp_i2c8";
1385 drive-strength = <16>;
1386 bias-disable;
1387 };
1388
1389 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1390 pins = "gpio6", "gpio7";
1391 function = "gpio";
1392 drive-strength = <2>;
1393 bias-disable;
1394 };
1395
1396 blsp1_i2c6_default: blsp1-i2c6-state {
1397 pins = "gpio27", "gpio28";
1398 function = "blsp_i2c6";
1399 drive-strength = <16>;
1400 bias-disable;
1401 };
1402
1403 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1404 pins = "gpio27", "gpio28";
1405 function = "gpio";
1406 drive-strength = <2>;
1407 bias-pull-up;
1408 };
1409
1410 cci0_default: cci0-default-state {
1411 pins = "gpio17", "gpio18";
1412 function = "cci_i2c";
1413 drive-strength = <16>;
1414 bias-disable;
1415 };
1416
1417 camera0_state_on:
1418 camera_rear_default: camera-rear-default-state {
1419 camera0_mclk: mclk0-pins {
1420 pins = "gpio13";
1421 function = "cam_mclk";
1422 drive-strength = <16>;
1423 bias-disable;
1424 };
1425
1426 camera0_rst: rst-pins {
1427 pins = "gpio25";
1428 function = "gpio";
1429 drive-strength = <16>;
1430 bias-disable;
1431 };
1432
1433 camera0_pwdn: pwdn-pins {
1434 pins = "gpio26";
1435 function = "gpio";
1436 drive-strength = <16>;
1437 bias-disable;
1438 };
1439 };
1440
1441 cci1_default: cci1-default-state {
1442 pins = "gpio19", "gpio20";
1443 function = "cci_i2c";
1444 drive-strength = <16>;
1445 bias-disable;
1446 };
1447
1448 camera1_state_on:
1449 camera_board_default: camera-board-default-state {
1450 mclk1-pins {
1451 pins = "gpio14";
1452 function = "cam_mclk";
1453 drive-strength = <16>;
1454 bias-disable;
1455 };
1456
1457 pwdn-pins {
1458 pins = "gpio98";
1459 function = "gpio";
1460 drive-strength = <16>;
1461 bias-disable;
1462 };
1463
1464 rst-pins {
1465 pins = "gpio104";
1466 function = "gpio";
1467 drive-strength = <16>;
1468 bias-disable;
1469 };
1470 };
1471
1472 camera2_state_on:
1473 camera_front_default: camera-front-default-state {
1474 camera2_mclk: mclk2-pins {
1475 pins = "gpio15";
1476 function = "cam_mclk";
1477 drive-strength = <16>;
1478 bias-disable;
1479 };
1480
1481 camera2_rst: rst-pins {
1482 pins = "gpio23";
1483 function = "gpio";
1484 drive-strength = <16>;
1485 bias-disable;
1486 };
1487
1488 pwdn-pins {
1489 pins = "gpio133";
1490 function = "gpio";
1491 drive-strength = <16>;
1492 bias-disable;
1493 };
1494 };
1495
1496 pcie0_state_on: pcie0-state-on-state {
1497 perst-pins {
1498 pins = "gpio35";
1499 function = "gpio";
1500 drive-strength = <2>;
1501 bias-pull-down;
1502 };
1503
1504 clkreq-pins {
1505 pins = "gpio36";
1506 function = "pci_e0";
1507 drive-strength = <2>;
1508 bias-pull-up;
1509 };
1510
1511 wake-pins {
1512 pins = "gpio37";
1513 function = "gpio";
1514 drive-strength = <2>;
1515 bias-pull-up;
1516 };
1517 };
1518
1519 pcie0_state_off: pcie0-state-off-state {
1520 perst-pins {
1521 pins = "gpio35";
1522 function = "gpio";
1523 drive-strength = <2>;
1524 bias-pull-down;
1525 };
1526
1527 clkreq-pins {
1528 pins = "gpio36";
1529 function = "gpio";
1530 drive-strength = <2>;
1531 bias-disable;
1532 };
1533
1534 wake-pins {
1535 pins = "gpio37";
1536 function = "gpio";
1537 drive-strength = <2>;
1538 bias-disable;
1539 };
1540 };
1541
1542 blsp1_uart2_default: blsp1-uart2-default-state {
1543 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1544 function = "blsp_uart2";
1545 drive-strength = <16>;
1546 bias-disable;
1547 };
1548
1549 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1550 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1551 function = "gpio";
1552 drive-strength = <2>;
1553 bias-disable;
1554 };
1555
1556 blsp1_i2c3_default: blsp1-i2c3-default-state {
1557 pins = "gpio47", "gpio48";
1558 function = "blsp_i2c3";
1559 drive-strength = <16>;
1560 bias-disable;
1561 };
1562
1563 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1564 pins = "gpio47", "gpio48";
1565 function = "gpio";
1566 drive-strength = <2>;
1567 bias-disable;
1568 };
1569
1570 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1571 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1572 function = "blsp_uart9";
1573 drive-strength = <16>;
1574 bias-disable;
1575 };
1576
1577 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1578 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1579 function = "blsp_uart9";
1580 drive-strength = <2>;
1581 bias-disable;
1582 };
1583
1584 blsp2_i2c3_default: blsp2-i2c3-state-state {
1585 pins = "gpio51", "gpio52";
1586 function = "blsp_i2c9";
1587 drive-strength = <16>;
1588 bias-disable;
1589 };
1590
1591 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1592 pins = "gpio51", "gpio52";
1593 function = "gpio";
1594 drive-strength = <2>;
1595 bias-disable;
1596 };
1597
1598 wcd_intr_default: wcd-intr-default-state {
1599 pins = "gpio54";
1600 function = "gpio";
1601 drive-strength = <2>;
1602 bias-pull-down;
1603 };
1604
1605 blsp2_i2c1_default: blsp2-i2c1-state {
1606 pins = "gpio55", "gpio56";
1607 function = "blsp_i2c7";
1608 drive-strength = <16>;
1609 bias-disable;
1610 };
1611
1612 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1613 pins = "gpio55", "gpio56";
1614 function = "gpio";
1615 drive-strength = <2>;
1616 bias-disable;
1617 };
1618
1619 blsp2_i2c5_default: blsp2-i2c5-state {
1620 pins = "gpio60", "gpio61";
1621 function = "blsp_i2c11";
1622 drive-strength = <2>;
1623 bias-disable;
1624 };
1625
1626 /* Sleep state for BLSP2_I2C5 is missing.. */
1627
1628 cdc_reset_active: cdc-reset-active-state {
1629 pins = "gpio64";
1630 function = "gpio";
1631 drive-strength = <16>;
1632 bias-pull-down;
1633 output-high;
1634 };
1635
1636 cdc_reset_sleep: cdc-reset-sleep-state {
1637 pins = "gpio64";
1638 function = "gpio";
1639 drive-strength = <16>;
1640 bias-disable;
1641 output-low;
1642 };
1643
1644 blsp2_spi6_default: blsp2-spi6-default-state {
1645 spi-pins {
1646 pins = "gpio85", "gpio86", "gpio88";
1647 function = "blsp_spi12";
1648 drive-strength = <12>;
1649 bias-disable;
1650 };
1651
1652 cs-pins {
1653 pins = "gpio87";
1654 function = "gpio";
1655 drive-strength = <16>;
1656 bias-disable;
1657 output-high;
1658 };
1659 };
1660
1661 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1662 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1663 function = "gpio";
1664 drive-strength = <2>;
1665 bias-pull-down;
1666 };
1667
1668 blsp2_i2c6_default: blsp2-i2c6-state {
1669 pins = "gpio87", "gpio88";
1670 function = "blsp_i2c12";
1671 drive-strength = <16>;
1672 bias-disable;
1673 };
1674
1675 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1676 pins = "gpio87", "gpio88";
1677 function = "gpio";
1678 drive-strength = <2>;
1679 bias-disable;
1680 };
1681
1682 pcie1_state_on: pcie1-on-state {
1683 perst-pins {
1684 pins = "gpio130";
1685 function = "gpio";
1686 drive-strength = <2>;
1687 bias-pull-down;
1688 };
1689
1690 clkreq-pins {
1691 pins = "gpio131";
1692 function = "pci_e1";
1693 drive-strength = <2>;
1694 bias-pull-up;
1695 };
1696
1697 wake-pins {
1698 pins = "gpio132";
1699 function = "gpio";
1700 drive-strength = <2>;
1701 bias-pull-down;
1702 };
1703 };
1704
1705 pcie1_state_off: pcie1-off-state {
1706 /* Perst is missing? */
1707 clkreq-pins {
1708 pins = "gpio131";
1709 function = "gpio";
1710 drive-strength = <2>;
1711 bias-disable;
1712 };
1713
1714 wake-pins {
1715 pins = "gpio132";
1716 function = "gpio";
1717 drive-strength = <2>;
1718 bias-disable;
1719 };
1720 };
1721
1722 pcie2_state_on: pcie2-on-state {
1723 perst-pins {
1724 pins = "gpio114";
1725 function = "gpio";
1726 drive-strength = <2>;
1727 bias-pull-down;
1728 };
1729
1730 clkreq-pins {
1731 pins = "gpio115";
1732 function = "pci_e2";
1733 drive-strength = <2>;
1734 bias-pull-up;
1735 };
1736
1737 wake-pins {
1738 pins = "gpio116";
1739 function = "gpio";
1740 drive-strength = <2>;
1741 bias-pull-down;
1742 };
1743 };
1744
1745 pcie2_state_off: pcie2-off-state {
1746 /* Perst is missing? */
1747 clkreq-pins {
1748 pins = "gpio115";
1749 function = "gpio";
1750 drive-strength = <2>;
1751 bias-disable;
1752 };
1753
1754 wake-pins {
1755 pins = "gpio116";
1756 function = "gpio";
1757 drive-strength = <2>;
1758 bias-disable;
1759 };
1760 };
1761
1762 sdc1_state_on: sdc1-on-state {
1763 clk-pins {
1764 pins = "sdc1_clk";
1765 bias-disable;
1766 drive-strength = <16>;
1767 };
1768
1769 cmd-pins {
1770 pins = "sdc1_cmd";
1771 bias-pull-up;
1772 drive-strength = <10>;
1773 };
1774
1775 data-pins {
1776 pins = "sdc1_data";
1777 bias-pull-up;
1778 drive-strength = <10>;
1779 };
1780
1781 rclk-pins {
1782 pins = "sdc1_rclk";
1783 bias-pull-down;
1784 };
1785 };
1786
1787 sdc1_state_off: sdc1-off-state {
1788 clk-pins {
1789 pins = "sdc1_clk";
1790 bias-disable;
1791 drive-strength = <2>;
1792 };
1793
1794 cmd-pins {
1795 pins = "sdc1_cmd";
1796 bias-pull-up;
1797 drive-strength = <2>;
1798 };
1799
1800 data-pins {
1801 pins = "sdc1_data";
1802 bias-pull-up;
1803 drive-strength = <2>;
1804 };
1805
1806 rclk-pins {
1807 pins = "sdc1_rclk";
1808 bias-pull-down;
1809 };
1810 };
1811
1812 sdc2_state_on: sdc2-on-state {
1813 clk-pins {
1814 pins = "sdc2_clk";
1815 bias-disable;
1816 drive-strength = <16>;
1817 };
1818
1819 cmd-pins {
1820 pins = "sdc2_cmd";
1821 bias-pull-up;
1822 drive-strength = <10>;
1823 };
1824
1825 data-pins {
1826 pins = "sdc2_data";
1827 bias-pull-up;
1828 drive-strength = <10>;
1829 };
1830 };
1831
1832 sdc2_state_off: sdc2-off-state {
1833 clk-pins {
1834 pins = "sdc2_clk";
1835 bias-disable;
1836 drive-strength = <2>;
1837 };
1838
1839 cmd-pins {
1840 pins = "sdc2_cmd";
1841 bias-pull-up;
1842 drive-strength = <2>;
1843 };
1844
1845 data-pins {
1846 pins = "sdc2_data";
1847 bias-pull-up;
1848 drive-strength = <2>;
1849 };
1850 };
1851 };
1852
1853 sram@290000 {
1854 compatible = "qcom,rpm-stats";
1855 reg = <0x00290000 0x10000>;
1856 };
1857
1858 spmi_bus: spmi@400f000 {
1859 compatible = "qcom,spmi-pmic-arb";
1860 reg = <0x0400f000 0x1000>,
1861 <0x04400000 0x800000>,
1862 <0x04c00000 0x800000>,
1863 <0x05800000 0x200000>,
1864 <0x0400a000 0x002100>;
1865 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1866 interrupt-names = "periph_irq";
1867 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1868 qcom,ee = <0>;
1869 qcom,channel = <0>;
1870 #address-cells = <2>;
1871 #size-cells = <0>;
1872 interrupt-controller;
1873 #interrupt-cells = <4>;
1874 };
1875
1876 bus@0 {
1877 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1878 compatible = "simple-pm-bus";
1879 #address-cells = <1>;
1880 #size-cells = <1>;
1881 ranges = <0x0 0x0 0xffffffff>;
1882
1883 pcie0: pcie@600000 {
1884 compatible = "qcom,pcie-msm8996";
1885 status = "disabled";
1886 power-domains = <&gcc PCIE0_GDSC>;
1887 bus-range = <0x00 0xff>;
1888 num-lanes = <1>;
1889
1890 reg = <0x00600000 0x2000>,
1891 <0x0c000000 0xf1d>,
1892 <0x0c000f20 0xa8>,
1893 <0x0c100000 0x100000>;
1894 reg-names = "parf", "dbi", "elbi","config";
1895
1896 phys = <&pciephy_0>;
1897 phy-names = "pciephy";
1898
1899 #address-cells = <3>;
1900 #size-cells = <2>;
1901 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1902 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1903
1904 device_type = "pci";
1905
1906 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1907 interrupt-names = "msi";
1908 #interrupt-cells = <1>;
1909 interrupt-map-mask = <0 0 0 0x7>;
1910 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1911 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1912 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1913 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1914
1915 pinctrl-names = "default", "sleep";
1916 pinctrl-0 = <&pcie0_state_on>;
1917 pinctrl-1 = <&pcie0_state_off>;
1918
1919 linux,pci-domain = <0>;
1920
1921 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1922 <&gcc GCC_PCIE_0_AUX_CLK>,
1923 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1924 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1925 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1926
1927 clock-names = "pipe",
1928 "aux",
1929 "cfg",
1930 "bus_master",
1931 "bus_slave";
1932 };
1933
1934 pcie1: pcie@608000 {
1935 compatible = "qcom,pcie-msm8996";
1936 power-domains = <&gcc PCIE1_GDSC>;
1937 bus-range = <0x00 0xff>;
1938 num-lanes = <1>;
1939
1940 status = "disabled";
1941
1942 reg = <0x00608000 0x2000>,
1943 <0x0d000000 0xf1d>,
1944 <0x0d000f20 0xa8>,
1945 <0x0d100000 0x100000>;
1946
1947 reg-names = "parf", "dbi", "elbi","config";
1948
1949 phys = <&pciephy_1>;
1950 phy-names = "pciephy";
1951
1952 #address-cells = <3>;
1953 #size-cells = <2>;
1954 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1955 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1956
1957 device_type = "pci";
1958
1959 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1960 interrupt-names = "msi";
1961 #interrupt-cells = <1>;
1962 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1967
1968 pinctrl-names = "default", "sleep";
1969 pinctrl-0 = <&pcie1_state_on>;
1970 pinctrl-1 = <&pcie1_state_off>;
1971
1972 linux,pci-domain = <1>;
1973
1974 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1975 <&gcc GCC_PCIE_1_AUX_CLK>,
1976 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1977 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1978 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1979
1980 clock-names = "pipe",
1981 "aux",
1982 "cfg",
1983 "bus_master",
1984 "bus_slave";
1985 };
1986
1987 pcie2: pcie@610000 {
1988 compatible = "qcom,pcie-msm8996";
1989 power-domains = <&gcc PCIE2_GDSC>;
1990 bus-range = <0x00 0xff>;
1991 num-lanes = <1>;
1992 status = "disabled";
1993 reg = <0x00610000 0x2000>,
1994 <0x0e000000 0xf1d>,
1995 <0x0e000f20 0xa8>,
1996 <0x0e100000 0x100000>;
1997
1998 reg-names = "parf", "dbi", "elbi","config";
1999
2000 phys = <&pciephy_2>;
2001 phy-names = "pciephy";
2002
2003 #address-cells = <3>;
2004 #size-cells = <2>;
2005 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
2006 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2007
2008 device_type = "pci";
2009
2010 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
2011 interrupt-names = "msi";
2012 #interrupt-cells = <1>;
2013 interrupt-map-mask = <0 0 0 0x7>;
2014 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2015 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2016 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2017 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2018
2019 pinctrl-names = "default", "sleep";
2020 pinctrl-0 = <&pcie2_state_on>;
2021 pinctrl-1 = <&pcie2_state_off>;
2022
2023 linux,pci-domain = <2>;
2024 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2025 <&gcc GCC_PCIE_2_AUX_CLK>,
2026 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2027 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2028 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2029
2030 clock-names = "pipe",
2031 "aux",
2032 "cfg",
2033 "bus_master",
2034 "bus_slave";
2035 };
2036 };
2037
2038 ufshc: ufshc@624000 {
2039 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2040 "jedec,ufs-2.0";
2041 reg = <0x00624000 0x2500>;
2042 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2043
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2044 phys = <&ufsphy>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2045 phy-names = "ufsphy";
2046
2047 power-domains = <&gcc UFS_GDSC>;
2048
2049 clock-names =
2050 "core_clk_src",
2051 "core_clk",
2052 "bus_clk",
2053 "bus_aggr_clk",
2054 "iface_clk",
2055 "core_clk_unipro_src",
2056 "core_clk_unipro",
2057 "core_clk_ice",
2058 "ref_clk",
2059 "tx_lane0_sync_clk",
2060 "rx_lane0_sync_clk";
2061 clocks =
2062 <&gcc UFS_AXI_CLK_SRC>,
2063 <&gcc GCC_UFS_AXI_CLK>,
2064 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2065 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2066 <&gcc GCC_UFS_AHB_CLK>,
2067 <&gcc UFS_ICE_CORE_CLK_SRC>,
2068 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2069 <&gcc GCC_UFS_ICE_CORE_CLK>,
2070 <&rpmcc RPM_SMD_LN_BB_CLK>,
2071 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2072 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2073 freq-table-hz =
2074 <100000000 200000000>,
2075 <0 0>,
2076 <0 0>,
2077 <0 0>,
2078 <0 0>,
2079 <150000000 300000000>,
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]2080 <75000000 150000000>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2081 <0 0>,
2082 <0 0>,
2083 <0 0>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2084 <0 0>;
2085
2086 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>,
2087 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>;
2088 interconnect-names = "ufs-ddr", "cpu-ufs";
2089
2090 lanes-per-direction = <1>;
2091 #reset-cells = <1>;
2092 status = "disabled";
2093 };
2094
2095 ufsphy: phy@627000 {
2096 compatible = "qcom,msm8996-qmp-ufs-phy";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2097 reg = <0x00627000 0x1000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2098
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]2099 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>;
2100 clock-names = "ref", "qref";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2101
2102 resets = <&ufshc 0>;
2103 reset-names = "ufsphy";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2104
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2105 #clock-cells = <1>;
2106 #phy-cells = <0>;
2107
2108 status = "disabled";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2109 };
2110
2111 camss: camss@a34000 {
2112 compatible = "qcom,msm8996-camss";
2113 reg = <0x00a34000 0x1000>,
2114 <0x00a00030 0x4>,
2115 <0x00a35000 0x1000>,
2116 <0x00a00038 0x4>,
2117 <0x00a36000 0x1000>,
2118 <0x00a00040 0x4>,
2119 <0x00a30000 0x100>,
2120 <0x00a30400 0x100>,
2121 <0x00a30800 0x100>,
2122 <0x00a30c00 0x100>,
2123 <0x00a31000 0x500>,
2124 <0x00a00020 0x10>,
2125 <0x00a10000 0x1000>,
2126 <0x00a14000 0x1000>;
2127 reg-names = "csiphy0",
2128 "csiphy0_clk_mux",
2129 "csiphy1",
2130 "csiphy1_clk_mux",
2131 "csiphy2",
2132 "csiphy2_clk_mux",
2133 "csid0",
2134 "csid1",
2135 "csid2",
2136 "csid3",
2137 "ispif",
2138 "csi_clk_mux",
2139 "vfe0",
2140 "vfe1";
2141 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2142 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2143 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2144 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2145 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2146 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2147 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2148 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2149 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2150 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2151 interrupt-names = "csiphy0",
2152 "csiphy1",
2153 "csiphy2",
2154 "csid0",
2155 "csid1",
2156 "csid2",
2157 "csid3",
2158 "ispif",
2159 "vfe0",
2160 "vfe1";
2161 power-domains = <&mmcc VFE0_GDSC>,
2162 <&mmcc VFE1_GDSC>;
2163 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2164 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2165 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2166 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2167 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2168 <&mmcc CAMSS_CSI0_AHB_CLK>,
2169 <&mmcc CAMSS_CSI0_CLK>,
2170 <&mmcc CAMSS_CSI0PHY_CLK>,
2171 <&mmcc CAMSS_CSI0PIX_CLK>,
2172 <&mmcc CAMSS_CSI0RDI_CLK>,
2173 <&mmcc CAMSS_CSI1_AHB_CLK>,
2174 <&mmcc CAMSS_CSI1_CLK>,
2175 <&mmcc CAMSS_CSI1PHY_CLK>,
2176 <&mmcc CAMSS_CSI1PIX_CLK>,
2177 <&mmcc CAMSS_CSI1RDI_CLK>,
2178 <&mmcc CAMSS_CSI2_AHB_CLK>,
2179 <&mmcc CAMSS_CSI2_CLK>,
2180 <&mmcc CAMSS_CSI2PHY_CLK>,
2181 <&mmcc CAMSS_CSI2PIX_CLK>,
2182 <&mmcc CAMSS_CSI2RDI_CLK>,
2183 <&mmcc CAMSS_CSI3_AHB_CLK>,
2184 <&mmcc CAMSS_CSI3_CLK>,
2185 <&mmcc CAMSS_CSI3PHY_CLK>,
2186 <&mmcc CAMSS_CSI3PIX_CLK>,
2187 <&mmcc CAMSS_CSI3RDI_CLK>,
2188 <&mmcc CAMSS_AHB_CLK>,
2189 <&mmcc CAMSS_VFE0_CLK>,
2190 <&mmcc CAMSS_CSI_VFE0_CLK>,
2191 <&mmcc CAMSS_VFE0_AHB_CLK>,
2192 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2193 <&mmcc CAMSS_VFE1_CLK>,
2194 <&mmcc CAMSS_CSI_VFE1_CLK>,
2195 <&mmcc CAMSS_VFE1_AHB_CLK>,
2196 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2197 <&mmcc CAMSS_VFE_AHB_CLK>,
2198 <&mmcc CAMSS_VFE_AXI_CLK>;
2199 clock-names = "top_ahb",
2200 "ispif_ahb",
2201 "csiphy0_timer",
2202 "csiphy1_timer",
2203 "csiphy2_timer",
2204 "csi0_ahb",
2205 "csi0",
2206 "csi0_phy",
2207 "csi0_pix",
2208 "csi0_rdi",
2209 "csi1_ahb",
2210 "csi1",
2211 "csi1_phy",
2212 "csi1_pix",
2213 "csi1_rdi",
2214 "csi2_ahb",
2215 "csi2",
2216 "csi2_phy",
2217 "csi2_pix",
2218 "csi2_rdi",
2219 "csi3_ahb",
2220 "csi3",
2221 "csi3_phy",
2222 "csi3_pix",
2223 "csi3_rdi",
2224 "ahb",
2225 "vfe0",
2226 "csi_vfe0",
2227 "vfe0_ahb",
2228 "vfe0_stream",
2229 "vfe1",
2230 "csi_vfe1",
2231 "vfe1_ahb",
2232 "vfe1_stream",
2233 "vfe_ahb",
2234 "vfe_axi";
2235 iommus = <&vfe_smmu 0>,
2236 <&vfe_smmu 1>,
2237 <&vfe_smmu 2>,
2238 <&vfe_smmu 3>;
2239 status = "disabled";
2240 ports {
2241 #address-cells = <1>;
2242 #size-cells = <0>;
2243 };
2244 };
2245
2246 cci: cci@a0c000 {
2247 compatible = "qcom,msm8996-cci";
2248 #address-cells = <1>;
2249 #size-cells = <0>;
2250 reg = <0xa0c000 0x1000>;
2251 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2252 power-domains = <&mmcc CAMSS_GDSC>;
2253 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2254 <&mmcc CAMSS_CCI_AHB_CLK>,
2255 <&mmcc CAMSS_CCI_CLK>,
2256 <&mmcc CAMSS_AHB_CLK>;
2257 clock-names = "camss_top_ahb",
2258 "cci_ahb",
2259 "cci",
2260 "camss_ahb";
2261 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2262 <&mmcc CAMSS_CCI_CLK>;
2263 assigned-clock-rates = <80000000>, <37500000>;
2264 pinctrl-names = "default";
2265 pinctrl-0 = <&cci0_default &cci1_default>;
2266 status = "disabled";
2267
2268 cci_i2c0: i2c-bus@0 {
2269 reg = <0>;
2270 clock-frequency = <400000>;
2271 #address-cells = <1>;
2272 #size-cells = <0>;
2273 };
2274
2275 cci_i2c1: i2c-bus@1 {
2276 reg = <1>;
2277 clock-frequency = <400000>;
2278 #address-cells = <1>;
2279 #size-cells = <0>;
2280 };
2281 };
2282
2283 adreno_smmu: iommu@b40000 {
2284 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2285 reg = <0x00b40000 0x10000>;
2286
2287 #global-interrupts = <1>;
2288 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2289 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2290 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2291 #iommu-cells = <1>;
2292
2293 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
2294 <&mmcc GPU_AHB_CLK>;
2295 clock-names = "bus", "iface";
2296
2297 power-domains = <&mmcc GPU_GDSC>;
2298 };
2299
2300 venus: video-codec@c00000 {
2301 compatible = "qcom,msm8996-venus";
2302 reg = <0x00c00000 0xff000>;
2303 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2304 power-domains = <&mmcc VENUS_GDSC>;
2305 clocks = <&mmcc VIDEO_CORE_CLK>,
2306 <&mmcc VIDEO_AHB_CLK>,
2307 <&mmcc VIDEO_AXI_CLK>,
2308 <&mmcc VIDEO_MAXI_CLK>;
2309 clock-names = "core", "iface", "bus", "mbus";
2310 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
2311 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
2312 interconnect-names = "video-mem", "cpu-cfg";
2313 iommus = <&venus_smmu 0x00>,
2314 <&venus_smmu 0x01>,
2315 <&venus_smmu 0x0a>,
2316 <&venus_smmu 0x07>,
2317 <&venus_smmu 0x0e>,
2318 <&venus_smmu 0x0f>,
2319 <&venus_smmu 0x08>,
2320 <&venus_smmu 0x09>,
2321 <&venus_smmu 0x0b>,
2322 <&venus_smmu 0x0c>,
2323 <&venus_smmu 0x0d>,
2324 <&venus_smmu 0x10>,
2325 <&venus_smmu 0x11>,
2326 <&venus_smmu 0x21>,
2327 <&venus_smmu 0x28>,
2328 <&venus_smmu 0x29>,
2329 <&venus_smmu 0x2b>,
2330 <&venus_smmu 0x2c>,
2331 <&venus_smmu 0x2d>,
2332 <&venus_smmu 0x31>;
2333 memory-region = <&venus_mem>;
2334 status = "disabled";
2335
2336 video-decoder {
2337 compatible = "venus-decoder";
2338 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2339 clock-names = "core";
2340 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2341 };
2342
2343 video-encoder {
2344 compatible = "venus-encoder";
2345 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2346 clock-names = "core";
2347 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2348 };
2349 };
2350
2351 mdp_smmu: iommu@d00000 {
2352 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2353 reg = <0x00d00000 0x10000>;
2354
2355 #global-interrupts = <1>;
2356 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2357 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2358 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2359 #iommu-cells = <1>;
2360 clocks = <&mmcc SMMU_MDP_AXI_CLK>,
2361 <&mmcc SMMU_MDP_AHB_CLK>;
2362 clock-names = "bus", "iface";
2363
2364 power-domains = <&mmcc MDSS_GDSC>;
2365 };
2366
2367 venus_smmu: iommu@d40000 {
2368 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2369 reg = <0x00d40000 0x20000>;
2370 #global-interrupts = <1>;
2371 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2374 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2375 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2376 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2377 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2378 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2379 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2380 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
2381 <&mmcc SMMU_VIDEO_AHB_CLK>;
2382 clock-names = "bus", "iface";
2383 #iommu-cells = <1>;
2384 status = "okay";
2385 };
2386
2387 vfe_smmu: iommu@da0000 {
2388 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2389 reg = <0x00da0000 0x10000>;
2390
2391 #global-interrupts = <1>;
2392 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2393 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2394 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2395 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2396 clocks = <&mmcc SMMU_VFE_AXI_CLK>,
2397 <&mmcc SMMU_VFE_AHB_CLK>;
2398 clock-names = "bus", "iface";
2399 #iommu-cells = <1>;
2400 };
2401
2402 lpass_q6_smmu: iommu@1600000 {
2403 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2404 reg = <0x01600000 0x20000>;
2405 #iommu-cells = <1>;
2406 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2407
2408 #global-interrupts = <1>;
2409 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2410 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2411 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2412 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2413 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2414 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2415 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2416 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2417 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2418 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2419 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2420 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2421 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2422
2423 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
2424 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
2425 clock-names = "bus", "iface";
2426 };
2427
2428 slpi_pil: remoteproc@1c00000 {
2429 compatible = "qcom,msm8996-slpi-pil";
2430 reg = <0x01c00000 0x4000>;
2431
2432 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2433 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2434 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2435 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2436 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2437 interrupt-names = "wdog",
2438 "fatal",
2439 "ready",
2440 "handover",
2441 "stop-ack";
2442
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2443 clocks = <&xo_board>;
2444 clock-names = "xo";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2445
2446 memory-region = <&slpi_mem>;
2447
2448 qcom,smem-states = <&slpi_smp2p_out 0>;
2449 qcom,smem-state-names = "stop";
2450
2451 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2452 power-domain-names = "ssc_cx";
2453
2454 status = "disabled";
2455
2456 smd-edge {
2457 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
2458
2459 label = "dsps";
2460 mboxes = <&apcs_glb 25>;
2461 qcom,smd-edge = <3>;
2462 qcom,remote-pid = <3>;
2463 };
2464 };
2465
2466 mss_pil: remoteproc@2080000 {
2467 compatible = "qcom,msm8996-mss-pil";
2468 reg = <0x2080000 0x100>,
2469 <0x2180000 0x020>;
2470 reg-names = "qdsp6", "rmb";
2471
2472 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2473 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2474 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2475 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2476 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2477 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2478 interrupt-names = "wdog", "fatal", "ready",
2479 "handover", "stop-ack",
2480 "shutdown-ack";
2481
2482 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2483 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2484 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2485 <&xo_board>,
2486 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2487 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2488 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2489 <&rpmcc RPM_SMD_QDSS_CLK>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2490 clock-names = "iface",
2491 "bus",
2492 "mem",
2493 "xo",
2494 "gpll0_mss",
2495 "snoc_axi",
2496 "mnoc_axi",
2497 "qdss";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2498
2499 resets = <&gcc GCC_MSS_RESTART>;
2500 reset-names = "mss_restart";
2501
2502 power-domains = <&rpmpd MSM8996_VDDCX>,
2503 <&rpmpd MSM8996_VDDMX>;
2504 power-domain-names = "cx", "mx";
2505
2506 qcom,smem-states = <&mpss_smp2p_out 0>;
2507 qcom,smem-state-names = "stop";
2508
2509 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2510
2511 status = "disabled";
2512
2513 mba {
2514 memory-region = <&mba_mem>;
2515 };
2516
2517 mpss {
2518 memory-region = <&mpss_mem>;
2519 };
2520
2521 metadata {
2522 memory-region = <&mdata_mem>;
2523 };
2524
2525 smd-edge {
2526 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2527
2528 label = "mpss";
2529 mboxes = <&apcs_glb 12>;
2530 qcom,smd-edge = <0>;
2531 qcom,remote-pid = <1>;
2532 };
2533 };
2534
2535 stm@3002000 {
2536 compatible = "arm,coresight-stm", "arm,primecell";
2537 reg = <0x3002000 0x1000>,
2538 <0x8280000 0x180000>;
2539 reg-names = "stm-base", "stm-stimulus-base";
2540
2541 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2542 clock-names = "apb_pclk", "atclk";
2543
2544 out-ports {
2545 port {
2546 stm_out: endpoint {
2547 remote-endpoint =
2548 <&funnel0_in>;
2549 };
2550 };
2551 };
2552 };
2553
2554 tpiu@3020000 {
2555 compatible = "arm,coresight-tpiu", "arm,primecell";
2556 reg = <0x3020000 0x1000>;
2557
2558 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2559 clock-names = "apb_pclk", "atclk";
2560
2561 in-ports {
2562 port {
2563 tpiu_in: endpoint {
2564 remote-endpoint =
2565 <&replicator_out1>;
2566 };
2567 };
2568 };
2569 };
2570
2571 funnel@3021000 {
2572 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2573 reg = <0x3021000 0x1000>;
2574
2575 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2576 clock-names = "apb_pclk", "atclk";
2577
2578 in-ports {
2579 #address-cells = <1>;
2580 #size-cells = <0>;
2581
2582 port@7 {
2583 reg = <7>;
2584 funnel0_in: endpoint {
2585 remote-endpoint =
2586 <&stm_out>;
2587 };
2588 };
2589 };
2590
2591 out-ports {
2592 port {
2593 funnel0_out: endpoint {
2594 remote-endpoint =
2595 <&merge_funnel_in0>;
2596 };
2597 };
2598 };
2599 };
2600
2601 funnel@3022000 {
2602 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2603 reg = <0x3022000 0x1000>;
2604
2605 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2606 clock-names = "apb_pclk", "atclk";
2607
2608 in-ports {
2609 #address-cells = <1>;
2610 #size-cells = <0>;
2611
2612 port@6 {
2613 reg = <6>;
2614 funnel1_in: endpoint {
2615 remote-endpoint =
2616 <&apss_merge_funnel_out>;
2617 };
2618 };
2619 };
2620
2621 out-ports {
2622 port {
2623 funnel1_out: endpoint {
2624 remote-endpoint =
2625 <&merge_funnel_in1>;
2626 };
2627 };
2628 };
2629 };
2630
2631 funnel@3023000 {
2632 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2633 reg = <0x3023000 0x1000>;
2634
2635 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2636 clock-names = "apb_pclk", "atclk";
2637
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2638 in-ports {
2639 port {
2640 funnel_in2_in_modem_etm: endpoint {
2641 remote-endpoint =
2642 <&modem_etm_out_funnel_in2>;
2643 };
2644 };
2645 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2646
2647 out-ports {
2648 port {
2649 funnel2_out: endpoint {
2650 remote-endpoint =
2651 <&merge_funnel_in2>;
2652 };
2653 };
2654 };
2655 };
2656
2657 funnel@3025000 {
2658 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2659 reg = <0x3025000 0x1000>;
2660
2661 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2662 clock-names = "apb_pclk", "atclk";
2663
2664 in-ports {
2665 #address-cells = <1>;
2666 #size-cells = <0>;
2667
2668 port@0 {
2669 reg = <0>;
2670 merge_funnel_in0: endpoint {
2671 remote-endpoint =
2672 <&funnel0_out>;
2673 };
2674 };
2675
2676 port@1 {
2677 reg = <1>;
2678 merge_funnel_in1: endpoint {
2679 remote-endpoint =
2680 <&funnel1_out>;
2681 };
2682 };
2683
2684 port@2 {
2685 reg = <2>;
2686 merge_funnel_in2: endpoint {
2687 remote-endpoint =
2688 <&funnel2_out>;
2689 };
2690 };
2691 };
2692
2693 out-ports {
2694 port {
2695 merge_funnel_out: endpoint {
2696 remote-endpoint =
2697 <&etf_in>;
2698 };
2699 };
2700 };
2701 };
2702
2703 replicator@3026000 {
2704 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2705 reg = <0x3026000 0x1000>;
2706
2707 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2708 clock-names = "apb_pclk", "atclk";
2709
2710 in-ports {
2711 port {
2712 replicator_in: endpoint {
2713 remote-endpoint =
2714 <&etf_out>;
2715 };
2716 };
2717 };
2718
2719 out-ports {
2720 #address-cells = <1>;
2721 #size-cells = <0>;
2722
2723 port@0 {
2724 reg = <0>;
2725 replicator_out0: endpoint {
2726 remote-endpoint =
2727 <&etr_in>;
2728 };
2729 };
2730
2731 port@1 {
2732 reg = <1>;
2733 replicator_out1: endpoint {
2734 remote-endpoint =
2735 <&tpiu_in>;
2736 };
2737 };
2738 };
2739 };
2740
2741 etf@3027000 {
2742 compatible = "arm,coresight-tmc", "arm,primecell";
2743 reg = <0x3027000 0x1000>;
2744
2745 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2746 clock-names = "apb_pclk", "atclk";
2747
2748 in-ports {
2749 port {
2750 etf_in: endpoint {
2751 remote-endpoint =
2752 <&merge_funnel_out>;
2753 };
2754 };
2755 };
2756
2757 out-ports {
2758 port {
2759 etf_out: endpoint {
2760 remote-endpoint =
2761 <&replicator_in>;
2762 };
2763 };
2764 };
2765 };
2766
2767 etr@3028000 {
2768 compatible = "arm,coresight-tmc", "arm,primecell";
2769 reg = <0x3028000 0x1000>;
2770
2771 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2772 clock-names = "apb_pclk", "atclk";
2773 arm,scatter-gather;
2774
2775 in-ports {
2776 port {
2777 etr_in: endpoint {
2778 remote-endpoint =
2779 <&replicator_out0>;
2780 };
2781 };
2782 };
2783 };
2784
2785 debug@3810000 {
2786 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2787 reg = <0x3810000 0x1000>;
2788
2789 clocks = <&rpmcc RPM_QDSS_CLK>;
2790 clock-names = "apb_pclk";
2791
2792 cpu = <&CPU0>;
2793 };
2794
2795 etm@3840000 {
2796 compatible = "arm,coresight-etm4x", "arm,primecell";
2797 reg = <0x3840000 0x1000>;
2798
2799 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2800 clock-names = "apb_pclk", "atclk";
2801
2802 cpu = <&CPU0>;
2803
2804 out-ports {
2805 port {
2806 etm0_out: endpoint {
2807 remote-endpoint =
2808 <&apss_funnel0_in0>;
2809 };
2810 };
2811 };
2812 };
2813
2814 debug@3910000 {
2815 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2816 reg = <0x3910000 0x1000>;
2817
2818 clocks = <&rpmcc RPM_QDSS_CLK>;
2819 clock-names = "apb_pclk";
2820
2821 cpu = <&CPU1>;
2822 };
2823
2824 etm@3940000 {
2825 compatible = "arm,coresight-etm4x", "arm,primecell";
2826 reg = <0x3940000 0x1000>;
2827
2828 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2829 clock-names = "apb_pclk", "atclk";
2830
2831 cpu = <&CPU1>;
2832
2833 out-ports {
2834 port {
2835 etm1_out: endpoint {
2836 remote-endpoint =
2837 <&apss_funnel0_in1>;
2838 };
2839 };
2840 };
2841 };
2842
2843 funnel@39b0000 { /* APSS Funnel 0 */
2844 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2845 reg = <0x39b0000 0x1000>;
2846
2847 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2848 clock-names = "apb_pclk", "atclk";
2849
2850 in-ports {
2851 #address-cells = <1>;
2852 #size-cells = <0>;
2853
2854 port@0 {
2855 reg = <0>;
2856 apss_funnel0_in0: endpoint {
2857 remote-endpoint = <&etm0_out>;
2858 };
2859 };
2860
2861 port@1 {
2862 reg = <1>;
2863 apss_funnel0_in1: endpoint {
2864 remote-endpoint = <&etm1_out>;
2865 };
2866 };
2867 };
2868
2869 out-ports {
2870 port {
2871 apss_funnel0_out: endpoint {
2872 remote-endpoint =
2873 <&apss_merge_funnel_in0>;
2874 };
2875 };
2876 };
2877 };
2878
2879 debug@3a10000 {
2880 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2881 reg = <0x3a10000 0x1000>;
2882
2883 clocks = <&rpmcc RPM_QDSS_CLK>;
2884 clock-names = "apb_pclk";
2885
2886 cpu = <&CPU2>;
2887 };
2888
2889 etm@3a40000 {
2890 compatible = "arm,coresight-etm4x", "arm,primecell";
2891 reg = <0x3a40000 0x1000>;
2892
2893 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2894 clock-names = "apb_pclk", "atclk";
2895
2896 cpu = <&CPU2>;
2897
2898 out-ports {
2899 port {
2900 etm2_out: endpoint {
2901 remote-endpoint =
2902 <&apss_funnel1_in0>;
2903 };
2904 };
2905 };
2906 };
2907
2908 debug@3b10000 {
2909 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2910 reg = <0x3b10000 0x1000>;
2911
2912 clocks = <&rpmcc RPM_QDSS_CLK>;
2913 clock-names = "apb_pclk";
2914
2915 cpu = <&CPU3>;
2916 };
2917
2918 etm@3b40000 {
2919 compatible = "arm,coresight-etm4x", "arm,primecell";
2920 reg = <0x3b40000 0x1000>;
2921
2922 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2923 clock-names = "apb_pclk", "atclk";
2924
2925 cpu = <&CPU3>;
2926
2927 out-ports {
2928 port {
2929 etm3_out: endpoint {
2930 remote-endpoint =
2931 <&apss_funnel1_in1>;
2932 };
2933 };
2934 };
2935 };
2936
2937 funnel@3bb0000 { /* APSS Funnel 1 */
2938 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2939 reg = <0x3bb0000 0x1000>;
2940
2941 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2942 clock-names = "apb_pclk", "atclk";
2943
2944 in-ports {
2945 #address-cells = <1>;
2946 #size-cells = <0>;
2947
2948 port@0 {
2949 reg = <0>;
2950 apss_funnel1_in0: endpoint {
2951 remote-endpoint = <&etm2_out>;
2952 };
2953 };
2954
2955 port@1 {
2956 reg = <1>;
2957 apss_funnel1_in1: endpoint {
2958 remote-endpoint = <&etm3_out>;
2959 };
2960 };
2961 };
2962
2963 out-ports {
2964 port {
2965 apss_funnel1_out: endpoint {
2966 remote-endpoint =
2967 <&apss_merge_funnel_in1>;
2968 };
2969 };
2970 };
2971 };
2972
2973 funnel@3bc0000 {
2974 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2975 reg = <0x3bc0000 0x1000>;
2976
2977 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2978 clock-names = "apb_pclk", "atclk";
2979
2980 in-ports {
2981 #address-cells = <1>;
2982 #size-cells = <0>;
2983
2984 port@0 {
2985 reg = <0>;
2986 apss_merge_funnel_in0: endpoint {
2987 remote-endpoint =
2988 <&apss_funnel0_out>;
2989 };
2990 };
2991
2992 port@1 {
2993 reg = <1>;
2994 apss_merge_funnel_in1: endpoint {
2995 remote-endpoint =
2996 <&apss_funnel1_out>;
2997 };
2998 };
2999 };
3000
3001 out-ports {
3002 port {
3003 apss_merge_funnel_out: endpoint {
3004 remote-endpoint =
3005 <&funnel1_in>;
3006 };
3007 };
3008 };
3009 };
3010
3011 kryocc: clock-controller@6400000 {
3012 compatible = "qcom,msm8996-apcc";
3013 reg = <0x06400000 0x90000>;
3014
3015 clock-names = "xo", "sys_apcs_aux";
3016 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3017
3018 #clock-cells = <1>;
3019 };
3020
3021 usb3: usb@6af8800 {
3022 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3023 reg = <0x06af8800 0x400>;
3024 #address-cells = <1>;
3025 #size-cells = <1>;
3026 ranges;
3027
3028 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
3029 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
3030 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3031
3032 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3033 <&gcc GCC_USB30_MASTER_CLK>,
3034 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3035 <&gcc GCC_USB30_SLEEP_CLK>,
3036 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
3037 clock-names = "cfg_noc",
3038 "core",
3039 "iface",
3040 "sleep",
3041 "mock_utmi";
3042
3043 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3044 <&gcc GCC_USB30_MASTER_CLK>;
3045 assigned-clock-rates = <19200000>, <120000000>;
3046
3047 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
3048 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
3049 interconnect-names = "usb-ddr", "apps-usb";
3050
3051 power-domains = <&gcc USB30_GDSC>;
3052 status = "disabled";
3053
3054 usb3_dwc3: usb@6a00000 {
3055 compatible = "snps,dwc3";
3056 reg = <0x06a00000 0xcc00>;
3057 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3058 phys = <&hsusb_phy1>, <&usb3phy>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3059 phy-names = "usb2-phy", "usb3-phy";
3060 snps,hird-threshold = /bits/ 8 <0>;
3061 snps,dis_u2_susphy_quirk;
3062 snps,dis_enblslpm_quirk;
3063 snps,is-utmi-l1-suspend;
3064 tx-fifo-resize;
3065 };
3066 };
3067
3068 usb3phy: phy@7410000 {
3069 compatible = "qcom,msm8996-qmp-usb3-phy";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3070 reg = <0x07410000 0x1000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3071
3072 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3073 <&gcc GCC_USB3_CLKREF_CLK>,
3074 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3075 <&gcc GCC_USB3_PHY_PIPE_CLK>;
3076 clock-names = "aux",
3077 "ref",
3078 "cfg_ahb",
3079 "pipe";
3080 clock-output-names = "usb3_phy_pipe_clk_src";
3081 #clock-cells = <0>;
3082 #phy-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3083
3084 resets = <&gcc GCC_USB3_PHY_BCR>,
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3085 <&gcc GCC_USB3PHY_PHY_BCR>;
3086 reset-names = "phy",
3087 "phy_phy";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3088
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3089 status = "disabled";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3090 };
3091
3092 hsusb_phy1: phy@7411000 {
3093 compatible = "qcom,msm8996-qusb2-phy";
3094 reg = <0x07411000 0x180>;
3095 #phy-cells = <0>;
3096
3097 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3098 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3099 clock-names = "cfg_ahb", "ref";
3100
3101 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3102 nvmem-cells = <&qusb2p_hstx_trim>;
3103 status = "disabled";
3104 };
3105
3106 hsusb_phy2: phy@7412000 {
3107 compatible = "qcom,msm8996-qusb2-phy";
3108 reg = <0x07412000 0x180>;
3109 #phy-cells = <0>;
3110
3111 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3112 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3113 clock-names = "cfg_ahb", "ref";
3114
3115 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3116 nvmem-cells = <&qusb2s_hstx_trim>;
3117 status = "disabled";
3118 };
3119
3120 sdhc1: mmc@7464900 {
3121 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3122 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3123 reg-names = "hc", "core";
3124
3125 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3126 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3127 interrupt-names = "hc_irq", "pwr_irq";
3128
3129 clock-names = "iface", "core", "xo";
3130 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3131 <&gcc GCC_SDCC1_APPS_CLK>,
3132 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3133 resets = <&gcc GCC_SDCC1_BCR>;
3134
3135 pinctrl-names = "default", "sleep";
3136 pinctrl-0 = <&sdc1_state_on>;
3137 pinctrl-1 = <&sdc1_state_off>;
3138
3139 bus-width = <8>;
3140 non-removable;
3141 status = "disabled";
3142 };
3143
3144 sdhc2: mmc@74a4900 {
3145 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3146 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3147 reg-names = "hc", "core";
3148
3149 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3150 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3151 interrupt-names = "hc_irq", "pwr_irq";
3152
3153 clock-names = "iface", "core", "xo";
3154 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3155 <&gcc GCC_SDCC2_APPS_CLK>,
3156 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3157 resets = <&gcc GCC_SDCC2_BCR>;
3158
3159 pinctrl-names = "default", "sleep";
3160 pinctrl-0 = <&sdc2_state_on>;
3161 pinctrl-1 = <&sdc2_state_off>;
3162
3163 bus-width = <4>;
3164 status = "disabled";
3165 };
3166
3167 blsp1_dma: dma-controller@7544000 {
3168 compatible = "qcom,bam-v1.7.0";
3169 reg = <0x07544000 0x2b000>;
3170 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3171 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3172 clock-names = "bam_clk";
3173 qcom,controlled-remotely;
3174 #dma-cells = <1>;
3175 qcom,ee = <0>;
3176 };
3177
3178 blsp1_uart2: serial@7570000 {
3179 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3180 reg = <0x07570000 0x1000>;
3181 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3182 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3183 <&gcc GCC_BLSP1_AHB_CLK>;
3184 clock-names = "core", "iface";
3185 pinctrl-names = "default", "sleep";
3186 pinctrl-0 = <&blsp1_uart2_default>;
3187 pinctrl-1 = <&blsp1_uart2_sleep>;
3188 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3189 dma-names = "tx", "rx";
3190 status = "disabled";
3191 };
3192
3193 blsp1_spi1: spi@7575000 {
3194 compatible = "qcom,spi-qup-v2.2.1";
3195 reg = <0x07575000 0x600>;
3196 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3197 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3198 <&gcc GCC_BLSP1_AHB_CLK>;
3199 clock-names = "core", "iface";
3200 pinctrl-names = "default", "sleep";
3201 pinctrl-0 = <&blsp1_spi1_default>;
3202 pinctrl-1 = <&blsp1_spi1_sleep>;
3203 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3204 dma-names = "tx", "rx";
3205 #address-cells = <1>;
3206 #size-cells = <0>;
3207 status = "disabled";
3208 };
3209
3210 blsp1_i2c3: i2c@7577000 {
3211 compatible = "qcom,i2c-qup-v2.2.1";
3212 reg = <0x07577000 0x1000>;
3213 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3214 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3215 <&gcc GCC_BLSP1_AHB_CLK>;
3216 clock-names = "core", "iface";
3217 pinctrl-names = "default", "sleep";
3218 pinctrl-0 = <&blsp1_i2c3_default>;
3219 pinctrl-1 = <&blsp1_i2c3_sleep>;
3220 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3221 dma-names = "tx", "rx";
3222 #address-cells = <1>;
3223 #size-cells = <0>;
3224 status = "disabled";
3225 };
3226
3227 blsp1_i2c6: i2c@757a000 {
3228 compatible = "qcom,i2c-qup-v2.2.1";
3229 reg = <0x757a000 0x1000>;
3230 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
3231 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
3232 <&gcc GCC_BLSP1_AHB_CLK>;
3233 clock-names = "core", "iface";
3234 pinctrl-names = "default", "sleep";
3235 pinctrl-0 = <&blsp1_i2c6_default>;
3236 pinctrl-1 = <&blsp1_i2c6_sleep>;
3237 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
3238 dma-names = "tx", "rx";
3239 #address-cells = <1>;
3240 #size-cells = <0>;
3241 status = "disabled";
3242 };
3243
3244 blsp2_dma: dma-controller@7584000 {
3245 compatible = "qcom,bam-v1.7.0";
3246 reg = <0x07584000 0x2b000>;
3247 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3248 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3249 clock-names = "bam_clk";
3250 qcom,controlled-remotely;
3251 #dma-cells = <1>;
3252 qcom,ee = <0>;
3253 };
3254
3255 blsp2_uart2: serial@75b0000 {
3256 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3257 reg = <0x075b0000 0x1000>;
3258 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3259 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3260 <&gcc GCC_BLSP2_AHB_CLK>;
3261 clock-names = "core", "iface";
3262 status = "disabled";
3263 };
3264
3265 blsp2_uart3: serial@75b1000 {
3266 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3267 reg = <0x075b1000 0x1000>;
3268 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3269 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3270 <&gcc GCC_BLSP2_AHB_CLK>;
3271 clock-names = "core", "iface";
3272 status = "disabled";
3273 };
3274
3275 blsp2_i2c1: i2c@75b5000 {
3276 compatible = "qcom,i2c-qup-v2.2.1";
3277 reg = <0x075b5000 0x1000>;
3278 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3279 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3280 <&gcc GCC_BLSP2_AHB_CLK>;
3281 clock-names = "core", "iface";
3282 pinctrl-names = "default", "sleep";
3283 pinctrl-0 = <&blsp2_i2c1_default>;
3284 pinctrl-1 = <&blsp2_i2c1_sleep>;
3285 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3286 dma-names = "tx", "rx";
3287 #address-cells = <1>;
3288 #size-cells = <0>;
3289 status = "disabled";
3290 };
3291
3292 blsp2_i2c2: i2c@75b6000 {
3293 compatible = "qcom,i2c-qup-v2.2.1";
3294 reg = <0x075b6000 0x1000>;
3295 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3296 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3297 <&gcc GCC_BLSP2_AHB_CLK>;
3298 clock-names = "core", "iface";
3299 pinctrl-names = "default", "sleep";
3300 pinctrl-0 = <&blsp2_i2c2_default>;
3301 pinctrl-1 = <&blsp2_i2c2_sleep>;
3302 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3303 dma-names = "tx", "rx";
3304 #address-cells = <1>;
3305 #size-cells = <0>;
3306 status = "disabled";
3307 };
3308
3309 blsp2_i2c3: i2c@75b7000 {
3310 compatible = "qcom,i2c-qup-v2.2.1";
3311 reg = <0x075b7000 0x1000>;
3312 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3313 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3314 <&gcc GCC_BLSP2_AHB_CLK>;
3315 clock-names = "core", "iface";
3316 clock-frequency = <400000>;
3317 pinctrl-names = "default", "sleep";
3318 pinctrl-0 = <&blsp2_i2c3_default>;
3319 pinctrl-1 = <&blsp2_i2c3_sleep>;
3320 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
3321 dma-names = "tx", "rx";
3322 #address-cells = <1>;
3323 #size-cells = <0>;
3324 status = "disabled";
3325 };
3326
3327 blsp2_i2c5: i2c@75b9000 {
3328 compatible = "qcom,i2c-qup-v2.2.1";
3329 reg = <0x75b9000 0x1000>;
3330 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3331 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3332 <&gcc GCC_BLSP2_AHB_CLK>;
3333 clock-names = "core", "iface";
3334 pinctrl-names = "default";
3335 pinctrl-0 = <&blsp2_i2c5_default>;
3336 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3337 dma-names = "tx", "rx";
3338 #address-cells = <1>;
3339 #size-cells = <0>;
3340 status = "disabled";
3341 };
3342
3343 blsp2_i2c6: i2c@75ba000 {
3344 compatible = "qcom,i2c-qup-v2.2.1";
3345 reg = <0x75ba000 0x1000>;
3346 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3347 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3348 <&gcc GCC_BLSP2_AHB_CLK>;
3349 clock-names = "core", "iface";
3350 pinctrl-names = "default", "sleep";
3351 pinctrl-0 = <&blsp2_i2c6_default>;
3352 pinctrl-1 = <&blsp2_i2c6_sleep>;
3353 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3354 dma-names = "tx", "rx";
3355 #address-cells = <1>;
3356 #size-cells = <0>;
3357 status = "disabled";
3358 };
3359
3360 blsp2_spi6: spi@75ba000 {
3361 compatible = "qcom,spi-qup-v2.2.1";
3362 reg = <0x075ba000 0x600>;
3363 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3364 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3365 <&gcc GCC_BLSP2_AHB_CLK>;
3366 clock-names = "core", "iface";
3367 pinctrl-names = "default", "sleep";
3368 pinctrl-0 = <&blsp2_spi6_default>;
3369 pinctrl-1 = <&blsp2_spi6_sleep>;
3370 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3371 dma-names = "tx", "rx";
3372 #address-cells = <1>;
3373 #size-cells = <0>;
3374 status = "disabled";
3375 };
3376
3377 usb2: usb@76f8800 {
3378 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3379 reg = <0x076f8800 0x400>;
3380 #address-cells = <1>;
3381 #size-cells = <1>;
3382 ranges;
3383
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]3384 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
3385 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
3386 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
3387 interrupt-names = "pwr_event",
3388 "qusb2_phy",
3389 "hs_phy_irq";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3390
3391 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3392 <&gcc GCC_USB20_MASTER_CLK>,
3393 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3394 <&gcc GCC_USB20_SLEEP_CLK>,
3395 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3396 clock-names = "cfg_noc",
3397 "core",
3398 "iface",
3399 "sleep",
3400 "mock_utmi";
3401
3402 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3403 <&gcc GCC_USB20_MASTER_CLK>;
3404 assigned-clock-rates = <19200000>, <60000000>;
3405
3406 power-domains = <&gcc USB30_GDSC>;
3407 qcom,select-utmi-as-pipe-clk;
3408 status = "disabled";
3409
3410 usb2_dwc3: usb@7600000 {
3411 compatible = "snps,dwc3";
3412 reg = <0x07600000 0xcc00>;
3413 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3414 phys = <&hsusb_phy2>;
3415 phy-names = "usb2-phy";
3416 maximum-speed = "high-speed";
3417 snps,dis_u2_susphy_quirk;
3418 snps,dis_enblslpm_quirk;
3419 };
3420 };
3421
3422 slimbam: dma-controller@9184000 {
3423 compatible = "qcom,bam-v1.7.0";
3424 qcom,controlled-remotely;
3425 reg = <0x09184000 0x32000>;
3426 num-channels = <31>;
3427 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3428 #dma-cells = <1>;
3429 qcom,ee = <1>;
3430 qcom,num-ees = <2>;
3431 };
3432
3433 slim_msm: slim-ngd@91c0000 {
3434 compatible = "qcom,slim-ngd-v1.5.0";
3435 reg = <0x091c0000 0x2c000>;
3436 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3437 dmas = <&slimbam 3>, <&slimbam 4>;
3438 dma-names = "rx", "tx";
3439 #address-cells = <1>;
3440 #size-cells = <0>;
3441
3442 status = "disabled";
3443 };
3444
3445 adsp_pil: remoteproc@9300000 {
3446 compatible = "qcom,msm8996-adsp-pil";
3447 reg = <0x09300000 0x80000>;
3448
3449 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3450 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3451 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3452 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3453 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3454 interrupt-names = "wdog", "fatal", "ready",
3455 "handover", "stop-ack";
3456
3457 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3458 clock-names = "xo";
3459
3460 memory-region = <&adsp_mem>;
3461
3462 qcom,smem-states = <&adsp_smp2p_out 0>;
3463 qcom,smem-state-names = "stop";
3464
3465 power-domains = <&rpmpd MSM8996_VDDCX>;
3466 power-domain-names = "cx";
3467
3468 status = "disabled";
3469
3470 smd-edge {
3471 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3472
3473 label = "lpass";
3474 mboxes = <&apcs_glb 8>;
3475 qcom,smd-edge = <1>;
3476 qcom,remote-pid = <2>;
3477
3478 apr {
3479 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3480 compatible = "qcom,apr-v2";
3481 qcom,smd-channels = "apr_audio_svc";
3482 qcom,domain = <APR_DOMAIN_ADSP>;
3483 #address-cells = <1>;
3484 #size-cells = <0>;
3485
3486 service@3 {
3487 reg = <APR_SVC_ADSP_CORE>;
3488 compatible = "qcom,q6core";
3489 };
3490
3491 q6afe: service@4 {
3492 compatible = "qcom,q6afe";
3493 reg = <APR_SVC_AFE>;
3494 q6afedai: dais {
3495 compatible = "qcom,q6afe-dais";
3496 #address-cells = <1>;
3497 #size-cells = <0>;
3498 #sound-dai-cells = <1>;
3499 dai@1 {
3500 reg = <1>;
3501 };
3502 };
3503 };
3504
3505 q6asm: service@7 {
3506 compatible = "qcom,q6asm";
3507 reg = <APR_SVC_ASM>;
3508 q6asmdai: dais {
3509 compatible = "qcom,q6asm-dais";
3510 #address-cells = <1>;
3511 #size-cells = <0>;
3512 #sound-dai-cells = <1>;
3513 iommus = <&lpass_q6_smmu 1>;
3514 };
3515 };
3516
3517 q6adm: service@8 {
3518 compatible = "qcom,q6adm";
3519 reg = <APR_SVC_ADM>;
3520 q6routing: routing {
3521 compatible = "qcom,q6adm-routing";
3522 #sound-dai-cells = <0>;
3523 };
3524 };
3525 };
3526 };
3527 };
3528
3529 apcs_glb: mailbox@9820000 {
3530 compatible = "qcom,msm8996-apcs-hmss-global";
3531 reg = <0x09820000 0x1000>;
3532
3533 #mbox-cells = <1>;
3534 #clock-cells = <0>;
3535 };
3536
3537 timer@9840000 {
3538 #address-cells = <1>;
3539 #size-cells = <1>;
3540 ranges;
3541 compatible = "arm,armv7-timer-mem";
3542 reg = <0x09840000 0x1000>;
3543 clock-frequency = <19200000>;
3544
3545 frame@9850000 {
3546 frame-number = <0>;
3547 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3549 reg = <0x09850000 0x1000>,
3550 <0x09860000 0x1000>;
3551 };
3552
3553 frame@9870000 {
3554 frame-number = <1>;
3555 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3556 reg = <0x09870000 0x1000>;
3557 status = "disabled";
3558 };
3559
3560 frame@9880000 {
3561 frame-number = <2>;
3562 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3563 reg = <0x09880000 0x1000>;
3564 status = "disabled";
3565 };
3566
3567 frame@9890000 {
3568 frame-number = <3>;
3569 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3570 reg = <0x09890000 0x1000>;
3571 status = "disabled";
3572 };
3573
3574 frame@98a0000 {
3575 frame-number = <4>;
3576 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3577 reg = <0x098a0000 0x1000>;
3578 status = "disabled";
3579 };
3580
3581 frame@98b0000 {
3582 frame-number = <5>;
3583 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3584 reg = <0x098b0000 0x1000>;
3585 status = "disabled";
3586 };
3587
3588 frame@98c0000 {
3589 frame-number = <6>;
3590 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3591 reg = <0x098c0000 0x1000>;
3592 status = "disabled";
3593 };
3594 };
3595
3596 saw3: syscon@9a10000 {
3597 compatible = "syscon";
3598 reg = <0x09a10000 0x1000>;
3599 };
3600
3601 cbf: clock-controller@9a11000 {
3602 compatible = "qcom,msm8996-cbf";
3603 reg = <0x09a11000 0x10000>;
3604 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3605 #clock-cells = <0>;
3606 #interconnect-cells = <1>;
3607 };
3608
3609 intc: interrupt-controller@9bc0000 {
3610 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3611 #interrupt-cells = <3>;
3612 interrupt-controller;
3613 #redistributor-regions = <1>;
3614 redistributor-stride = <0x0 0x40000>;
3615 reg = <0x09bc0000 0x10000>,
3616 <0x09c00000 0x100000>;
3617 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3618 };
3619 };
3620
3621 sound: sound {
3622 };
3623
3624 thermal-zones {
3625 cpu0-thermal {
3626 polling-delay-passive = <250>;
3627 polling-delay = <1000>;
3628
3629 thermal-sensors = <&tsens0 3>;
3630
3631 trips {
3632 cpu0_alert0: trip-point0 {
3633 temperature = <75000>;
3634 hysteresis = <2000>;
3635 type = "passive";
3636 };
3637
3638 cpu0_crit: cpu-crit {
3639 temperature = <110000>;
3640 hysteresis = <2000>;
3641 type = "critical";
3642 };
3643 };
3644 };
3645
3646 cpu1-thermal {
3647 polling-delay-passive = <250>;
3648 polling-delay = <1000>;
3649
3650 thermal-sensors = <&tsens0 5>;
3651
3652 trips {
3653 cpu1_alert0: trip-point0 {
3654 temperature = <75000>;
3655 hysteresis = <2000>;
3656 type = "passive";
3657 };
3658
3659 cpu1_crit: cpu-crit {
3660 temperature = <110000>;
3661 hysteresis = <2000>;
3662 type = "critical";
3663 };
3664 };
3665 };
3666
3667 cpu2-thermal {
3668 polling-delay-passive = <250>;
3669 polling-delay = <1000>;
3670
3671 thermal-sensors = <&tsens0 8>;
3672
3673 trips {
3674 cpu2_alert0: trip-point0 {
3675 temperature = <75000>;
3676 hysteresis = <2000>;
3677 type = "passive";
3678 };
3679
3680 cpu2_crit: cpu-crit {
3681 temperature = <110000>;
3682 hysteresis = <2000>;
3683 type = "critical";
3684 };
3685 };
3686 };
3687
3688 cpu3-thermal {
3689 polling-delay-passive = <250>;
3690 polling-delay = <1000>;
3691
3692 thermal-sensors = <&tsens0 10>;
3693
3694 trips {
3695 cpu3_alert0: trip-point0 {
3696 temperature = <75000>;
3697 hysteresis = <2000>;
3698 type = "passive";
3699 };
3700
3701 cpu3_crit: cpu-crit {
3702 temperature = <110000>;
3703 hysteresis = <2000>;
3704 type = "critical";
3705 };
3706 };
3707 };
3708
3709 gpu-top-thermal {
3710 polling-delay-passive = <250>;
3711 polling-delay = <1000>;
3712
3713 thermal-sensors = <&tsens1 6>;
3714
3715 trips {
3716 gpu1_alert0: trip-point0 {
3717 temperature = <90000>;
3718 hysteresis = <2000>;
3719 type = "passive";
3720 };
3721 };
3722
3723 cooling-maps {
3724 map0 {
3725 trip = <&gpu1_alert0>;
3726 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3727 };
3728 };
3729 };
3730
3731 gpu-bottom-thermal {
3732 polling-delay-passive = <250>;
3733 polling-delay = <1000>;
3734
3735 thermal-sensors = <&tsens1 7>;
3736
3737 trips {
3738 gpu2_alert0: trip-point0 {
3739 temperature = <90000>;
3740 hysteresis = <2000>;
3741 type = "passive";
3742 };
3743 };
3744
3745 cooling-maps {
3746 map0 {
3747 trip = <&gpu2_alert0>;
3748 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3749 };
3750 };
3751 };
3752
3753 m4m-thermal {
3754 polling-delay-passive = <250>;
3755 polling-delay = <1000>;
3756
3757 thermal-sensors = <&tsens0 1>;
3758
3759 trips {
3760 m4m_alert0: trip-point0 {
3761 temperature = <90000>;
3762 hysteresis = <2000>;
3763 type = "hot";
3764 };
3765 };
3766 };
3767
3768 l3-or-venus-thermal {
3769 polling-delay-passive = <250>;
3770 polling-delay = <1000>;
3771
3772 thermal-sensors = <&tsens0 2>;
3773
3774 trips {
3775 l3_or_venus_alert0: trip-point0 {
3776 temperature = <90000>;
3777 hysteresis = <2000>;
3778 type = "hot";
3779 };
3780 };
3781 };
3782
3783 cluster0-l2-thermal {
3784 polling-delay-passive = <250>;
3785 polling-delay = <1000>;
3786
3787 thermal-sensors = <&tsens0 7>;
3788
3789 trips {
3790 cluster0_l2_alert0: trip-point0 {
3791 temperature = <90000>;
3792 hysteresis = <2000>;
3793 type = "hot";
3794 };
3795 };
3796 };
3797
3798 cluster1-l2-thermal {
3799 polling-delay-passive = <250>;
3800 polling-delay = <1000>;
3801
3802 thermal-sensors = <&tsens0 12>;
3803
3804 trips {
3805 cluster1_l2_alert0: trip-point0 {
3806 temperature = <90000>;
3807 hysteresis = <2000>;
3808 type = "hot";
3809 };
3810 };
3811 };
3812
3813 camera-thermal {
3814 polling-delay-passive = <250>;
3815 polling-delay = <1000>;
3816
3817 thermal-sensors = <&tsens1 1>;
3818
3819 trips {
3820 camera_alert0: trip-point0 {
3821 temperature = <90000>;
3822 hysteresis = <2000>;
3823 type = "hot";
3824 };
3825 };
3826 };
3827
3828 q6-dsp-thermal {
3829 polling-delay-passive = <250>;
3830 polling-delay = <1000>;
3831
3832 thermal-sensors = <&tsens1 2>;
3833
3834 trips {
3835 q6_dsp_alert0: trip-point0 {
3836 temperature = <90000>;
3837 hysteresis = <2000>;
3838 type = "hot";
3839 };
3840 };
3841 };
3842
3843 mem-thermal {
3844 polling-delay-passive = <250>;
3845 polling-delay = <1000>;
3846
3847 thermal-sensors = <&tsens1 3>;
3848
3849 trips {
3850 mem_alert0: trip-point0 {
3851 temperature = <90000>;
3852 hysteresis = <2000>;
3853 type = "hot";
3854 };
3855 };
3856 };
3857
3858 modemtx-thermal {
3859 polling-delay-passive = <250>;
3860 polling-delay = <1000>;
3861
3862 thermal-sensors = <&tsens1 4>;
3863
3864 trips {
3865 modemtx_alert0: trip-point0 {
3866 temperature = <90000>;
3867 hysteresis = <2000>;
3868 type = "hot";
3869 };
3870 };
3871 };
3872 };
3873
3874 timer {
3875 compatible = "arm,armv8-timer";
3876 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3877 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3878 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3879 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3880 };
3881};