blob: 8971f7aa16a1458fcfb520ddfb7994e906f597b5 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -07002/*
3 * Copyright (c) 2012-2016 Toradex, Inc.
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -07004 */
5
Simon Glass0f2af882020-05-10 11:40:05 -06006#include <log.h>
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -07007#include <asm/io.h>
8#include <asm/arch-tegra/tegra_i2c.h>
Simon Glassdbd79542020-05-10 11:40:11 -06009#include <linux/delay.h>
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070010
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020011/* AS3722-PMIC-specific early init regs */
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070012
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020013#define AS3722_I2C_ADDR 0x80
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070014
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020015#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
16#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
17#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
18#define AS3722_SDCONTROL_REG 0x4D
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070019
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020020#define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */
21#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
22#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */
23#define AS3722_LDCONTROL_REG 0x4E
24
25#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
26#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
27
28#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
29#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070030
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020031#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
32#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
33
34#define AS3722_LDO1CONTROL_DATA (0x0200 | AS3722_LDCONTROL_REG)
35#define AS3722_LDO1VOLTAGE_DATA (0x7F00 | AS3722_LDO1VOLTAGE_REG)
36
37#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
38#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
39
40#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
41#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
42
43/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070044
45void pmic_enable_cpu_vdd(void)
46{
47 debug("%s entry\n", __func__);
48
49#ifdef AS3722_SD1VOLTAGE_DATA
50 /* Set up VDD_CORE, for boards where OTP is incorrect*/
51 debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
52 /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020053 tegra_i2c_ll_write(AS3722_I2C_ADDR,
54 AS3722_SD1VOLTAGE_DATA);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070055 /*
56 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
57 * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
58 */
59 udelay(10 * 1000);
60#endif
61
Dominik Sliwa3f6a2e22019-08-01 11:06:39 +030062 /*
63 * Make sure all non-fused regulators are down.
64 * That way we're in known state after software reboot from linux
65 */
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020066 tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0003);
Dominik Sliwa3f6a2e22019-08-01 11:06:39 +030067 udelay(10 * 1000);
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020068 tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0004);
Dominik Sliwa3f6a2e22019-08-01 11:06:39 +030069 udelay(10 * 1000);
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020070 tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x001b);
Dominik Sliwa3f6a2e22019-08-01 11:06:39 +030071 udelay(10 * 1000);
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020072 tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0014);
Dominik Sliwa3f6a2e22019-08-01 11:06:39 +030073 udelay(10 * 1000);
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020074 tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x001a);
Dominik Sliwa3f6a2e22019-08-01 11:06:39 +030075 udelay(10 * 1000);
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020076 tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0019);
Dominik Sliwa3f6a2e22019-08-01 11:06:39 +030077 udelay(10 * 1000);
78
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070079 debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
80 /*
81 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
82 * First set VDD to 1.0V, then enable the VDD regulator.
83 */
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020084 tegra_i2c_ll_write(AS3722_I2C_ADDR,
85 AS3722_SD0VOLTAGE_DATA);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070086 /*
87 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
88 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
89 */
90 udelay(10 * 1000);
91
92 debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
93 /*
94 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
95 * First set VDD to 1.0V, then enable the VDD regulator.
96 */
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +020097 tegra_i2c_ll_write(AS3722_I2C_ADDR,
98 AS3722_SD6VOLTAGE_DATA);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070099 /*
100 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
101 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
102 */
103 udelay(10 * 1000);
104
105 debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
106 /*
107 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
108 * First set VDD to 1.2V, then enable the VDD regulator.
109 */
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +0200110 tegra_i2c_ll_write(AS3722_I2C_ADDR,
111 AS3722_LDO2VOLTAGE_DATA);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700112 /*
113 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
114 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
115 */
116 udelay(10 * 1000);
117
118 debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
119 /*
120 * Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
121 * First set it to value closest to 3.3V, then enable the regulator
122 *
123 * NOTE: We do this early because doing it later seems to hose the CPU
124 * power rail/partition startup. Need to debug.
125 */
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +0200126 tegra_i2c_ll_write(AS3722_I2C_ADDR,
127 AS3722_LDO1VOLTAGE_DATA);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700128 /*
129 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
130 * tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
131 */
132 udelay(10 * 1000);
133
134 debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
135 /*
136 * Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
137 * First set it to bypass 3.3V straight thru, then enable the regulator
138 *
139 * NOTE: We do this early because doing it later seems to hose the CPU
140 * power rail/partition startup. Need to debug.
141 */
Svyatoslav Ryhel9e1ba0a2023-02-14 19:35:33 +0200142 tegra_i2c_ll_write(AS3722_I2C_ADDR,
143 AS3722_LDO6VOLTAGE_DATA);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700144 /*
145 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
146 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
147 */
148 udelay(10 * 1000);
149}