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Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2020 Broadcom.
4 *
5 */
6
Rayagonda Kokatanur237417d2020-07-15 22:49:04 +05307#include <fdt_support.h>
Tom Rinidec7ea02024-05-20 13:35:03 -06008#include <linux/errno.h>
Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +05309#include <asm/io.h>
Rayagonda Kokatanur73069ca2020-07-15 22:49:01 +053010#include <asm/gic-v3.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060011#include <asm/global_data.h>
Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +053012#include <asm/system.h>
13#include <asm/armv8/mmu.h>
Abhishek Shaha2936da2020-07-15 22:48:59 +053014#include <asm/arch-bcmns3/bl33_info.h>
Rayagonda Kokatanur237417d2020-07-15 22:49:04 +053015#include <dt-bindings/memory/bcm-ns3-mc.h>
Rayagonda Kokatanur6d7656e2020-08-25 23:16:37 +053016#include <broadcom/chimp.h>
Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +053017
Rayagonda Kokatanur237417d2020-07-15 22:49:04 +053018#define BANK_OFFSET(bank) ((u64)BCM_NS3_DDR_INFO_BASE + 8 + ((bank) * 16))
19
20/*
21 * ns3_dram_bank - DDR bank details
22 *
23 * @start: DDR bank start address
24 * @len: DDR bank length
25 */
26struct ns3_dram_bank {
27 u64 start[BCM_NS3_MAX_NR_BANKS];
28 u64 len[BCM_NS3_MAX_NR_BANKS];
29};
30
31/*
32 * ns3_dram_hdr - DDR header info
33 *
34 * @sig: DDR info signature
35 * @bank: DDR bank details
36 */
37struct ns3_dram_hdr {
38 u32 sig;
39 struct ns3_dram_bank bank;
40};
41
Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +053042static struct mm_region ns3_mem_map[] = {
43 {
44 .virt = 0x0UL,
45 .phys = 0x0UL,
46 .size = 0x80000000UL,
47 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
48 PTE_BLOCK_NON_SHARE |
49 PTE_BLOCK_PXN | PTE_BLOCK_UXN
50 }, {
Rayagonda Kokatanur237417d2020-07-15 22:49:04 +053051 .virt = BCM_NS3_MEM_START,
52 .phys = BCM_NS3_MEM_START,
53 .size = BCM_NS3_MEM_LEN,
Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +053054 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
55 PTE_BLOCK_INNER_SHARE
56 }, {
Rayagonda Kokatanur237417d2020-07-15 22:49:04 +053057 .virt = BCM_NS3_BANK_1_MEM_START,
58 .phys = BCM_NS3_BANK_1_MEM_START,
59 .size = BCM_NS3_BANK_1_MEM_LEN,
60 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
61 PTE_BLOCK_INNER_SHARE
62 }, {
Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +053063 /* List terminator */
64 0,
65 }
66};
67
68struct mm_region *mem_map = ns3_mem_map;
69
70DECLARE_GLOBAL_DATA_PTR;
71
Abhishek Shaha2936da2020-07-15 22:48:59 +053072/*
73 * Force the bl33_info to the data-section, as .bss will not be valid
74 * when save_boot_params is invoked.
75 */
76struct bl33_info *bl33_info __section(".data");
77
Rayagonda Kokatanur237417d2020-07-15 22:49:04 +053078/*
79 * Run modulo 256 checksum calculation and return the calculated checksum
80 */
81static u8 checksum_calc(u8 *p, unsigned int len)
82{
83 unsigned int i;
84 u8 chksum = 0;
85
86 for (i = 0; i < len; i++)
87 chksum += p[i];
88
89 return chksum;
90}
91
92/*
93 * This function parses the memory layout information from a reserved area in
94 * DDR, and then fix up the FDT before passing it to Linux.
95 *
96 * In the case of error, do nothing and the default memory layout in DT will
97 * be used
98 */
99static int mem_info_parse_fixup(void *fdt)
100{
101 struct ns3_dram_hdr hdr;
102 u32 *p32, i, nr_banks;
103 u64 *p64;
104
105 /* validate signature */
106 p32 = (u32 *)BCM_NS3_DDR_INFO_BASE;
107 hdr.sig = *p32;
108 if (hdr.sig != BCM_NS3_DDR_INFO_SIG) {
109 printf("DDR info signature 0x%x invalid\n", hdr.sig);
110 return -EINVAL;
111 }
112
113 /* run checksum test to validate data */
114 if (checksum_calc((u8 *)p32, BCM_NS3_DDR_INFO_LEN) != 0) {
115 printf("Checksum on DDR info failed\n");
116 return -EINVAL;
117 }
118
119 /* parse information for each bank */
120 nr_banks = 0;
121 for (i = 0; i < BCM_NS3_MAX_NR_BANKS; i++) {
122 /* skip banks with a length of zero */
123 p64 = (u64 *)BANK_OFFSET(i);
124 if (*(p64 + 1) == 0)
125 continue;
126
127 hdr.bank.start[i] = *p64;
128 hdr.bank.len[i] = *(p64 + 1);
129
130 printf("mem[%u] 0x%llx - 0x%llx\n", i, hdr.bank.start[i],
131 hdr.bank.start[i] + hdr.bank.len[i] - 1);
132 nr_banks++;
133 }
134
135 if (!nr_banks) {
136 printf("No DDR banks detected\n");
137 return -ENOMEM;
138 }
139
140 return fdt_fixup_memory_banks(fdt, hdr.bank.start, hdr.bank.len,
141 nr_banks);
142}
143
Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +0530144int board_init(void)
145{
Bharat Kumar Reddy Gootyffc76042020-07-15 22:49:05 +0530146 /* Setup memory using "memory" node from DTB */
147 if (fdtdec_setup_mem_size_base() != 0)
148 return -EINVAL;
149 fdtdec_setup_memory_banksize();
150
Abhishek Shaha2936da2020-07-15 22:48:59 +0530151 if (bl33_info->version != BL33_INFO_VERSION)
152 printf("*** warning: ATF BL31 and U-Boot not in sync! ***\n");
Simon Glass75e39122023-02-05 15:36:18 -0700153#if IS_ENABLED(CONFIG_BNXT_ETH)
Bharat Gooty08f2b5a2021-11-08 14:46:11 -0800154 if (chimp_fastboot_optee() != 0)
155 printf("*** warning: secure chimp fastboot failed! ***\n");
156#endif
Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +0530157 return 0;
158}
159
160int board_late_init(void)
161{
162 return 0;
163}
164
165int dram_init(void)
166{
Bharat Kumar Reddy Gootyffc76042020-07-15 22:49:05 +0530167 /*
168 * Mark ram base as the last 16MB of 2GB DDR, which is 0xFF00_0000.
169 * So that relocation happens with in the last 16MB memory.
170 */
171 gd->ram_base = (phys_size_t)(BCM_NS3_MEM_END - SZ_16M);
172 gd->ram_size = (unsigned long)SZ_16M;
Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +0530173
174 return 0;
175}
176
177int dram_init_banksize(void)
178{
Bharat Kumar Reddy Gootyffc76042020-07-15 22:49:05 +0530179 gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
180 gd->bd->bi_dram[0].size = SZ_16M;
Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +0530181
182 return 0;
183}
184
Bharat Kumar Reddy Gootyffc76042020-07-15 22:49:05 +0530185/* Limit RAM used by U-Boot to the DDR first bank End region */
Heinrich Schuchardt51a9aac2023-08-12 20:16:58 +0200186phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
Bharat Kumar Reddy Gootyffc76042020-07-15 22:49:05 +0530187{
188 return BCM_NS3_MEM_END;
189}
190
Harald Seiler6f14d5f2020-12-15 16:47:52 +0100191void reset_cpu(void)
Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +0530192{
Harald Seiler2cfae262020-12-15 16:47:50 +0100193 /* Perform a level 3 reset */
194 psci_system_reset2(3, 0);
Rayagonda Kokatanur1d8fa362020-07-15 22:48:55 +0530195}
Rayagonda Kokatanur73069ca2020-07-15 22:49:01 +0530196
197#ifdef CONFIG_OF_BOARD_SETUP
198int ft_board_setup(void *fdt, struct bd_info *bd)
199{
Rayagonda Kokatanur6d7656e2020-08-25 23:16:37 +0530200 u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT;
201
Michael Walle29b1d332021-10-27 18:54:54 +0200202 /* FIXME: Need to call gic_lpi_tables_init correctly now */
203 printf("%s: failed to init gic-lpi-tables\n", __func__);
Rayagonda Kokatanur73069ca2020-07-15 22:49:01 +0530204
Rayagonda Kokatanur6d7656e2020-08-25 23:16:37 +0530205 /*
206 * Check for chimp handshake status.
207 * Zero timeout value will actually fall to default timeout.
208 *
209 * System boot is independent of chimp handshake.
210 * chimp handshake failure is not a catastrophic error.
211 * Hence continue booting if chimp handshake fails.
212 */
213 chimp_handshake_status_optee(0, &chimp_hs);
214 if (chimp_hs == CHIMP_HANDSHAKE_SUCCESS)
215 printf("ChiMP handshake successful\n");
216 else
217 printf("ERROR: ChiMP handshake status 0x%x\n", chimp_hs);
218
Rayagonda Kokatanur237417d2020-07-15 22:49:04 +0530219 return mem_info_parse_fixup(fdt);
Rayagonda Kokatanur73069ca2020-07-15 22:49:01 +0530220}
221#endif /* CONFIG_OF_BOARD_SETUP */