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Laurentiu Tudor7690ea72019-07-30 17:29:58 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
Tom Rinidec7ea02024-05-20 13:35:03 -06006#include <config.h>
Laurentiu Tudor7690ea72019-07-30 17:29:58 +03007#include <asm/arch-fsl-layerscape/immap_lsch3.h>
8#include <asm/arch-fsl-layerscape/fsl_icid.h>
9#include <asm/arch-fsl-layerscape/fsl_portals.h>
Tom Rinidec7ea02024-05-20 13:35:03 -060010#include <asm/arch/stream_id_lsch3.h>
Laurentiu Tudor7690ea72019-07-30 17:29:58 +030011
12struct icid_id_table icid_tbl[] = {
Laurentiu Tudor01dc5472019-07-30 17:29:59 +030013 SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
Laurentiu Tudor7690ea72019-07-30 17:29:58 +030014 SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
15 SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
16 SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
Laurentiu Tudor0b1d35c2019-10-18 09:01:52 +000017#ifdef CONFIG_FSL_CAAM
Laurentiu Tudor7690ea72019-07-30 17:29:58 +030018 SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
19 SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
20 SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
21 SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
22 SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
23 SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
24 SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
25 SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
26 SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
27 SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
28 SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
29 SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
Laurentiu Tudor0b1d35c2019-10-18 09:01:52 +000030#endif
Laurentiu Tudor7690ea72019-07-30 17:29:58 +030031};
32
33int icid_tbl_sz = ARRAY_SIZE(icid_tbl);