wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 1 | /* |
| 2 | * board/mx1ads/mx1ads.c |
wdenk | 9e930b6 | 2004-06-19 21:19:10 +0000 | [diff] [blame] | 3 | * |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 4 | * (c) Copyright 2004 |
| 5 | * Techware Information Technology, Inc. |
| 6 | * http://www.techware.com.tw/ |
| 7 | * |
| 8 | * Ming-Len Wu <minglen_wu@techware.com.tw> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 26 | #include <common.h> |
Ben Warren | 3bf5d83 | 2009-08-25 13:09:37 -0700 | [diff] [blame] | 27 | #include <netdev.h> |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 28 | /*#include <mc9328.h>*/ |
wdenk | f9c57a2 | 2005-04-03 14:26:46 +0000 | [diff] [blame] | 29 | #include <asm/arch/imx-regs.h> |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 30 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 31 | DECLARE_GLOBAL_DATA_PTR; |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 32 | |
| 33 | #define FCLK_SPEED 1 |
| 34 | |
| 35 | #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ |
| 36 | #define M_MDIV 0xC3 |
| 37 | #define M_PDIV 0x4 |
| 38 | #define M_SDIV 0x1 |
| 39 | #elif FCLK_SPEED==1 /* Fout = 202.8MHz */ |
| 40 | #define M_MDIV 0xA1 |
| 41 | #define M_PDIV 0x3 |
| 42 | #define M_SDIV 0x1 |
| 43 | #endif |
| 44 | |
| 45 | #define USB_CLOCK 1 |
| 46 | |
| 47 | #if USB_CLOCK==0 |
| 48 | #define U_M_MDIV 0xA1 |
| 49 | #define U_M_PDIV 0x3 |
| 50 | #define U_M_SDIV 0x1 |
| 51 | #elif USB_CLOCK==1 |
| 52 | #define U_M_MDIV 0x48 |
| 53 | #define U_M_PDIV 0x3 |
| 54 | #define U_M_SDIV 0x2 |
| 55 | #endif |
| 56 | |
| 57 | #if 0 |
| 58 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 59 | static inline void delay (unsigned long loops) |
| 60 | { |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 61 | __asm__ volatile ("1:\n" |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 62 | "subs %0, %1, #1\n" |
| 63 | "bne 1b":"=r" (loops):"0" (loops)); |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 64 | } |
| 65 | |
wdenk | 9e930b6 | 2004-06-19 21:19:10 +0000 | [diff] [blame] | 66 | #endif |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * Miscellaneous platform dependent initialisations |
| 70 | */ |
| 71 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 72 | void SetAsynchMode (void) |
| 73 | { |
| 74 | __asm__ ("mrc p15,0,r0,c1,c0,0 \n" |
| 75 | "mov r2, #0xC0000000 \n" |
| 76 | "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n"); |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 77 | } |
wdenk | 9e930b6 | 2004-06-19 21:19:10 +0000 | [diff] [blame] | 78 | |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 79 | static u32 mc9328sid; |
| 80 | |
Fabio Estevam | 0856664 | 2011-06-11 15:16:32 +0000 | [diff] [blame] | 81 | int board_early_init_f(void) |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 82 | { |
| 83 | volatile unsigned int tmp; |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 84 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 85 | mc9328sid = SIDR; |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 86 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 87 | GPCR = 0x000003AB; /* I/O pad driving strength */ |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 88 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 89 | /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ |
| 90 | /* MX1_CS1L = 0x11110601; */ |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 91 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 92 | MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 93 | |
| 94 | /* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and |
| 95 | * BCLK divider to 2 (i.e. BCLK to 48 MHz) |
| 96 | */ |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 97 | CSCR = 0xAF000403; |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 98 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 99 | CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ |
| 100 | CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 101 | |
| 102 | /* setup cs4 for cs8900 ethernet */ |
wdenk | 9e930b6 | 2004-06-19 21:19:10 +0000 | [diff] [blame] | 103 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 104 | CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ |
| 105 | CS4L = 0x00001501; |
wdenk | 9e930b6 | 2004-06-19 21:19:10 +0000 | [diff] [blame] | 106 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 107 | GIUS (0) &= 0xFF3FFFFF; |
| 108 | GPR (0) &= 0xFF3FFFFF; |
wdenk | 9e930b6 | 2004-06-19 21:19:10 +0000 | [diff] [blame] | 109 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 110 | tmp = *(unsigned int *) (0x1500000C); |
| 111 | tmp = *(unsigned int *) (0x1500000C); |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 112 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 113 | SetAsynchMode (); |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 114 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 115 | icache_enable (); |
| 116 | dcache_enable (); |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 117 | |
| 118 | /* set PERCLKs */ |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 119 | PCDR = 0x00000055; /* set PERCLKS */ |
wdenk | 9e930b6 | 2004-06-19 21:19:10 +0000 | [diff] [blame] | 120 | |
| 121 | /* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes |
| 122 | * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 123 | * all sources selected as normal interrupt |
| 124 | */ |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 125 | |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 126 | /* MX1_INTTYPEH = 0; |
| 127 | MX1_INTTYPEL = 0; |
| 128 | */ |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 129 | return 0; |
| 130 | } |
| 131 | |
Fabio Estevam | 0856664 | 2011-06-11 15:16:32 +0000 | [diff] [blame] | 132 | int board_init(void) |
| 133 | { |
| 134 | gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; |
| 135 | |
| 136 | gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ |
| 137 | |
| 138 | return 0; |
| 139 | } |
| 140 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 141 | int board_late_init (void) |
| 142 | { |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 143 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 144 | setenv ("stdout", "serial"); |
| 145 | setenv ("stderr", "serial"); |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 146 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 147 | switch (mc9328sid) { |
| 148 | case 0x0005901d: |
| 149 | printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n", |
| 150 | mc9328sid); |
| 151 | break; |
| 152 | case 0x04d4c01d: |
| 153 | printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n", |
| 154 | mc9328sid); |
| 155 | break; |
| 156 | case 0x00d4c01d: |
| 157 | printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n", |
| 158 | mc9328sid); |
| 159 | break; |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 160 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 161 | default: |
| 162 | printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n", |
| 163 | mc9328sid); |
| 164 | break; |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 165 | } |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 166 | return 0; |
wdenk | 9e930b6 | 2004-06-19 21:19:10 +0000 | [diff] [blame] | 167 | } |
| 168 | |
Fabio Estevam | 0856664 | 2011-06-11 15:16:32 +0000 | [diff] [blame] | 169 | int dram_init(void) |
| 170 | { |
| 171 | /* dram_init must store complete ramsize in gd->ram_size */ |
Albert ARIBAUD | a960673 | 2011-07-03 05:55:33 +0000 | [diff] [blame^] | 172 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, |
Fabio Estevam | 0856664 | 2011-06-11 15:16:32 +0000 | [diff] [blame] | 173 | PHYS_SDRAM_1_SIZE); |
| 174 | return 0; |
| 175 | } |
| 176 | |
| 177 | void dram_init_banksize(void) |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 178 | { |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 179 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 180 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
wdenk | 9f664dd | 2004-06-09 21:50:45 +0000 | [diff] [blame] | 181 | } |
Ben Warren | 3bf5d83 | 2009-08-25 13:09:37 -0700 | [diff] [blame] | 182 | |
| 183 | #ifdef CONFIG_CMD_NET |
| 184 | int board_eth_init(bd_t *bis) |
| 185 | { |
| 186 | int rc = 0; |
| 187 | #ifdef CONFIG_CS8900 |
| 188 | rc = cs8900_initialize(0, CONFIG_CS8900_BASE); |
| 189 | #endif |
| 190 | return rc; |
| 191 | } |
| 192 | #endif |