blob: 949b57c24e0f49162206a9638fd194a5205a58e7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
York Sun7b08d212014-06-23 15:15:56 -07002/*
3 * Copyright 2014 Freescale Semiconductor
York Sun7b08d212014-06-23 15:15:56 -07004 */
5#include <common.h>
6#include <malloc.h>
7#include <errno.h>
Simon Glass0c364412019-12-28 10:44:48 -07008#include <net.h>
York Sun7b08d212014-06-23 15:15:56 -07009#include <netdev.h>
10#include <fsl_ifc.h>
11#include <fsl_ddr.h>
12#include <asm/io.h>
13#include <fdt_support.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090014#include <linux/libfdt.h>
J. German Rivera43e4ae32015-01-06 13:19:02 -080015#include <fsl-mc/fsl_mc.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060016#include <env_internal.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080017#include <asm/arch/soc.h>
York Sun7b08d212014-06-23 15:15:56 -070018
19DECLARE_GLOBAL_DATA_PTR;
20
21int board_init(void)
22{
23 init_final_memctl_regs();
Prabhakar Kushwahacf329182014-07-14 17:15:44 +053024
25#ifdef CONFIG_ENV_IS_NOWHERE
26 gd->env_addr = (ulong)&default_environment[0];
27#endif
28
York Sun7b08d212014-06-23 15:15:56 -070029 return 0;
30}
31
32int board_early_init_f(void)
33{
Scott Woodf64c98c2015-03-20 19:28:12 -070034 fsl_lsch3_early_init_f();
York Sun7b08d212014-06-23 15:15:56 -070035 return 0;
36}
37
York Sunc7a0e302014-08-13 10:21:05 -070038void detail_board_ddr_info(void)
39{
40 puts("\nDDR ");
41 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
42 print_ddr_info(0);
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053043#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Suncbe8e1c2016-04-04 11:41:26 -070044 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
York Sunc7a0e302014-08-13 10:21:05 -070045 puts("\nDP-DDR ");
46 print_size(gd->bd->bi_dram[2].size, "");
47 print_ddr_info(CONFIG_DP_DDR_CTRL);
48 }
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053049#endif
York Sunc7a0e302014-08-13 10:21:05 -070050}
51
Bhupesh Sharma25b8efe2015-03-19 09:20:43 -070052#if defined(CONFIG_ARCH_MISC_INIT)
53int arch_misc_init(void)
54{
Bhupesh Sharma25b8efe2015-03-19 09:20:43 -070055 return 0;
56}
57#endif
58
York Sun7b08d212014-06-23 15:15:56 -070059int board_eth_init(bd_t *bis)
60{
61 int error = 0;
62
63#ifdef CONFIG_SMC91111
64 error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
65#endif
66
Santan Kumar1afa9002017-05-05 15:42:29 +053067#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
York Sun7b08d212014-06-23 15:15:56 -070068 error = cpu_eth_init(bis);
69#endif
70 return error;
71}
72
Santan Kumar1afa9002017-05-05 15:42:29 +053073#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
York Sun7b08d212014-06-23 15:15:56 -070074void fdt_fixup_board_enet(void *fdt)
75{
76 int offset;
77
Stuart Yodera3466152016-03-02 16:37:13 -060078 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
J. German Rivera43e4ae32015-01-06 13:19:02 -080079
80 /*
81 * TODO: Remove this when backward compatibility
Stuart Yodera3466152016-03-02 16:37:13 -060082 * with old DT node (/fsl-mc) is no longer needed.
J. German Rivera43e4ae32015-01-06 13:19:02 -080083 */
84 if (offset < 0)
Stuart Yodera3466152016-03-02 16:37:13 -060085 offset = fdt_path_offset(fdt, "/fsl-mc");
J. German Rivera43e4ae32015-01-06 13:19:02 -080086
87 if (offset < 0) {
88 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
89 __func__, offset);
90 return;
91 }
92
Mian Yousaf Kaukab97124652018-12-18 14:01:17 +010093 if (get_mc_boot_status() == 0 &&
94 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
York Sun7b08d212014-06-23 15:15:56 -070095 fdt_status_okay(fdt, offset);
96 else
97 fdt_status_fail(fdt, offset);
98}
Alexander Graf2ebeb442016-11-17 01:02:57 +010099
100void board_quiesce_devices(void)
101{
102 fsl_mc_ldpaa_exit(gd->bd);
103}
York Sun7b08d212014-06-23 15:15:56 -0700104#endif
105
106#ifdef CONFIG_OF_BOARD_SETUP
Simon Glass2aec3cc2014-10-23 18:58:47 -0600107int ft_board_setup(void *blob, bd_t *bd)
York Sun7b08d212014-06-23 15:15:56 -0700108{
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530109 u64 base[CONFIG_NR_DRAM_BANKS];
110 u64 size[CONFIG_NR_DRAM_BANKS];
York Sun7b08d212014-06-23 15:15:56 -0700111
York Sun290a83a2014-09-08 12:20:01 -0700112 ft_cpu_setup(blob, bd);
113
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530114 /* fixup DT for the two GPP DDR banks */
115 base[0] = gd->bd->bi_dram[0].start;
116 size[0] = gd->bd->bi_dram[0].size;
117 base[1] = gd->bd->bi_dram[1].start;
118 size[1] = gd->bd->bi_dram[1].size;
119
York Sun4de24ef2017-03-06 09:02:28 -0800120#ifdef CONFIG_RESV_RAM
121 /* reduce size if reserved memory is within this bank */
122 if (gd->arch.resv_ram >= base[0] &&
123 gd->arch.resv_ram < base[0] + size[0])
124 size[0] = gd->arch.resv_ram - base[0];
125 else if (gd->arch.resv_ram >= base[1] &&
126 gd->arch.resv_ram < base[1] + size[1])
127 size[1] = gd->arch.resv_ram - base[1];
128#endif
129
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530130 fdt_fixup_memory_banks(blob, base, size, 2);
York Sun7b08d212014-06-23 15:15:56 -0700131
Nipun Guptad6912642018-08-20 16:01:14 +0530132 fdt_fsl_mc_fixup_iommu_map_entry(blob);
133
Santan Kumar1afa9002017-05-05 15:42:29 +0530134#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
York Sun7b08d212014-06-23 15:15:56 -0700135 fdt_fixup_board_enet(blob);
136#endif
Simon Glass2aec3cc2014-10-23 18:58:47 -0600137
138 return 0;
York Sun7b08d212014-06-23 15:15:56 -0700139}
140#endif
Bogdan Purcareata08bc0142017-05-24 16:40:21 +0000141
142#if defined(CONFIG_RESET_PHY_R)
143void reset_phy(void)
144{
145}
146#endif
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000147
148#ifdef CONFIG_TFABOOT
149void *env_sf_get_env_addr(void)
150{
151 return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET);
152}
153#endif