Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / a944fc1c3200d41eb2bdc90a8fd98106dc7044a2 / . / arch / arm / include / asm / arch-mx25 / clock.h
blob: 3045b78d08f41e26431ada62b7bc683618658c6f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
John Rigby9c146032010-01-25 23:12:56 -0700[diff] [blame]2/*
3 *
4 * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
5 *
6 * Modified for mx25 by John Rigby <jrigby@gmail.com>
John Rigby9c146032010-01-25 23:12:56 -0700[diff] [blame]7 */
8
9#ifndef __ASM_ARCH_CLOCK_H
10#define __ASM_ARCH_CLOCK_H
11
Benoît Thébaudeaud2dd29d2012-08-21 11:05:12 +0000[diff] [blame]12#ifdef CONFIG_MX25_HCLK_FREQ
13#define MXC_HCLK CONFIG_MX25_HCLK_FREQ
14#else
15#define MXC_HCLK 24000000
16#endif
17
18#ifdef CONFIG_MX25_CLK32
19#define MXC_CLK32 CONFIG_MX25_CLK32
20#else
21#define MXC_CLK32 32768
22#endif
23
Timo Ketola738fa8d2012-04-18 22:55:28 +0000[diff] [blame]24enum mxc_clock {
Benoît Thébaudeau05dd78f2012-09-27 10:27:28 +0000[diff] [blame]25 /* PER clocks (do not change order) */
Timo Ketola738fa8d2012-04-18 22:55:28 +0000[diff] [blame]26 MXC_CSI_CLK,
27 MXC_EPIT_CLK,
28 MXC_ESAI_CLK,
29 MXC_ESDHC1_CLK,
30 MXC_ESDHC2_CLK,
31 MXC_GPT_CLK,
32 MXC_I2C_CLK,
33 MXC_LCDC_CLK,
34 MXC_NFC_CLK,
35 MXC_OWIRE_CLK,
36 MXC_PWM_CLK,
37 MXC_SIM1_CLK,
38 MXC_SIM2_CLK,
39 MXC_SSI1_CLK,
40 MXC_SSI2_CLK,
41 MXC_UART_CLK,
Benoît Thébaudeau05dd78f2012-09-27 10:27:28 +0000[diff] [blame]42 /* Other clocks */
Timo Ketola738fa8d2012-04-18 22:55:28 +0000[diff] [blame]43 MXC_ARM_CLK,
Benoît Thébaudeau05dd78f2012-09-27 10:27:28 +0000[diff] [blame]44 MXC_AHB_CLK,
45 MXC_IPG_CLK,
46 MXC_CSPI_CLK,
Timo Ketola738fa8d2012-04-18 22:55:28 +0000[diff] [blame]47 MXC_FEC_CLK,
48 MXC_CLK_NUM
49};
50
Benoît Thébaudeau9d694242017-05-03 11:59:05 +0200[diff] [blame]51int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq);
Timo Ketola738fa8d2012-04-18 22:55:28 +0000[diff] [blame]52unsigned int mxc_get_clock(enum mxc_clock clk);
John Rigby9c146032010-01-25 23:12:56 -0700[diff] [blame]53
Benoît Thébaudeaub3ab1392012-09-27 10:27:57 +0000[diff] [blame]54#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK)
55#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
56
John Rigby9c146032010-01-25 23:12:56 -0700[diff] [blame]57#endif /* __ASM_ARCH_CLOCK_H */