Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 1 | |
| 2 | |
| 3 | U-Boot for Wind River SBC834x Boards |
| 4 | ==================================== |
| 5 | |
| 6 | |
| 7 | The Wind River SBC834x board is a 6U form factor (not CPCI) reference |
| 8 | design that uses the MPC8347E or MPC8349E processor. U-Boot support |
| 9 | for this board is heavily based on the existing U-Boot support for |
| 10 | Freescale MPC8349 reference boards. |
| 11 | |
| 12 | Support has been primarily tested on the SBC8349 version of the board, |
| 13 | although earlier versions were also tested on the SBC8347. The primary |
| 14 | difference in the two is the level of PCI functionality. |
| 15 | |
| 16 | http://www.windriver.com/products/OCD/SBC8347E_49E/ |
| 17 | |
| 18 | |
| 19 | Flash Details: |
| 20 | ============== |
| 21 | |
| 22 | The flash type is intel 28F640Jx (4096x16) [one device]. Base address |
| 23 | is 0xFF80_0000 which is also where the Hardware Reset Configuration |
Paul Gortmaker | 80b4bb7 | 2009-07-23 17:10:55 -0400 | [diff] [blame] | 24 | Word (HRCW) is stored. Caution should be used to not reset the |
| 25 | board without having a valid HRCW in place (i.e. erased flash) as |
| 26 | then a Wind River ICE will be required to restore the HRCW and flash |
| 27 | image. |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 28 | |
| 29 | |
| 30 | Restoring a corrupted or missing flash image: |
| 31 | ============================================= |
| 32 | |
Paul Gortmaker | 80b4bb7 | 2009-07-23 17:10:55 -0400 | [diff] [blame] | 33 | Note that U-boot versions up to and including 2009.06 had essentially |
| 34 | two copies of u-boot in flash; one at the very beginning, which set |
| 35 | the HRCW, and one at the very end, which was the image that was run. |
| 36 | As of this point in time, the two have been combined into just one |
| 37 | at the beginning of flash, which provides both the HRCW, and the image |
| 38 | that is executed. This frees up the remainder of flash for other uses. |
| 39 | Use of the u-boot command "fli" will indicate what parts are in use. |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 40 | Details for storing U-boot to flash using a Wind River ICE can be found |
| 41 | on page 19 of the board manual (request ERG-00328-001). The following |
| 42 | is a summary of that information: |
| 43 | |
| 44 | - Connect ICE and establish connection to it from WorkBench/OCD. |
| 45 | - Ensure you have background mode (BKM) in the OCD terminal window. |
| 46 | - Select the appropriate flash type (listed above) |
| 47 | - Prepare a u-boot image by using the Wind River Convert utility; |
| 48 | by using "Convert and Add file" on the ELF file from your build. |
Paul Gortmaker | 80b4bb7 | 2009-07-23 17:10:55 -0400 | [diff] [blame] | 49 | Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are |
| 50 | trying to preserve your old environment settings and user flash). |
| 51 | - Set the start address of the erase/flash process to FF80_0000 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 52 | - Set the target RAM required to 64kB. |
| 53 | - Select sectors for erasing (see note on enviroment below) |
| 54 | - Select Erase and Reprogram. |
| 55 | |
| 56 | Note that some versions of the register files used with Workbench |
| 57 | would zero some TSEC registers, which inhibits ethernet operation |
| 58 | by u-boot when this register file is played to the target. Using |
| 59 | "INN" in the OCD terminal window instead of "IN" before the "GO" |
| 60 | will not play the register file, and allow u-boot to use the TSEC |
| 61 | interface while executed from the ICE "GO" command. |
| 62 | |
| 63 | Alternatively, you can locate the register file which will be named |
| 64 | WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines |
| 65 | beginning with "SCGA TSEC1" and "SCGA TSEC2". This allows you to |
| 66 | use all the remaining register file content. |
| 67 | |
| 68 | If you wish to preserve your prior U-Boot environment settings, |
Paul Gortmaker | 80b4bb7 | 2009-07-23 17:10:55 -0400 | [diff] [blame] | 69 | then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF. |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 70 | The size for converting (and erasing) must be at least as large |
| 71 | as u-boot.bin. |
| 72 | |
| 73 | |
| 74 | Updating U-Boot with U-Boot: |
| 75 | ============================ |
| 76 | |
| 77 | This procedure is very similar to other boards that have u-boot installed. |
| 78 | Assuming that the network has been configured, and that the new u-boot.bin |
| 79 | has been copied to the TFTP server, the commands are: |
| 80 | |
| 81 | tftp 200000 u-boot.bin |
| 82 | protect off all |
Paul Gortmaker | 80b4bb7 | 2009-07-23 17:10:55 -0400 | [diff] [blame] | 83 | erase ff800000 ff83ffff |
| 84 | cp.b 200000 ff800000 40000 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 85 | protect on all |
| 86 | |
Paul Gortmaker | 80b4bb7 | 2009-07-23 17:10:55 -0400 | [diff] [blame] | 87 | You may wish to do a "md ff800000 20" operation as a prefix and postfix |
| 88 | to the above steps to inspect/compare the HRCW before/after as an extra |
| 89 | safety check before resetting the board upon completion of the reflash. |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 90 | |
| 91 | PCI: |
| 92 | ==== |
| 93 | |
| 94 | This board and U-Boot have been tested with PCI built in, on a SBC8349 |
| 95 | and confirmed that the "pci" command showed the intel e1000 that was |
| 96 | present in the PCI slot. Note that if a 33MHz 32bit card is inserted |
| 97 | in the slot, then the whole board will clock down to a 33MHz base |
| 98 | clock instead of the default 66MHz. This will change the baud clocks |
| 99 | and mess up your serial console output. If you want to use a 33MHz PCI |
| 100 | card, then you should build a U-Boot with #undef PCI_66M in the |
| 101 | include/configs/sbc8349.h and store this to flash prior to powering down |
| 102 | the board and inserting the 33MHz PCI card. |
| 103 | |
| 104 | By default PCI support is disabled to better support very early |
| 105 | revision MPC834x chips with possible PCI issues. Also PCI support is |
| 106 | untested on the sbc8347 variants at this point in time. |
| 107 | |
| 108 | |
| 109 | Paul Gortmaker, 01/2007 |