Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / a8c991617c2fd3109505b34457bbced8e43b0a2a / . / include / asm-m68k / immap_5445x.h
blob: d091d7b73c7f99719df28689783d12a27d3e496c [file] [log] [blame]
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]1/*
2 * MCF5445x Internal Memory Map
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __IMMAP_5445X__
27#define __IMMAP_5445X__
28
29/* Module Base Addresses */
30#define MMAP_SCM1 0xFC000000
31#define MMAP_XBS 0xFC004000
32#define MMAP_FBCS 0xFC008000
33#define MMAP_FEC0 0xFC030000
34#define MMAP_FEC1 0xFC034000
35#define MMAP_RTC 0xFC03C000
36#define MMAP_EDMA 0xFC044000
37#define MMAP_INTC0 0xFC048000
38#define MMAP_INTC1 0xFC04C000
39#define MMAP_IACK 0xFC054000
40#define MMAP_I2C 0xFC058000
41#define MMAP_DSPI 0xFC05C000
42#define MMAP_UART0 0xFC060000
43#define MMAP_UART1 0xFC064000
44#define MMAP_UART2 0xFC068000
45#define MMAP_DTMR0 0xFC070000
46#define MMAP_DTMR1 0xFC074000
47#define MMAP_DTMR2 0xFC078000
48#define MMAP_DTMR3 0xFC07C000
49#define MMAP_PIT0 0xFC080000
50#define MMAP_PIT1 0xFC084000
51#define MMAP_PIT2 0xFC088000
52#define MMAP_PIT3 0xFC08C000
53#define MMAP_EPORT 0xFC094000
54#define MMAP_WTM 0xFC098000
55#define MMAP_SBF 0xFC0A0000
56#define MMAP_RCM 0xFC0A0000
57#define MMAP_CCM 0xFC0A0000
58#define MMAP_GPIO 0xFC0A4000
59#define MMAP_PCI 0xFC0A8000
60#define MMAP_PCIARB 0xFC0AC000
61#define MMAP_RNG 0xFC0B4000
62#define MMAP_SDRAM 0xFC0B8000
63#define MMAP_SSI 0xFC0BC000
64#define MMAP_PLL 0xFC0C4000
65#define MMAP_ATA 0x90000000
66
67/*********************************************************************
68* ATA
69*********************************************************************/
70
71typedef struct atac {
72 /* PIO */
73 u8 toff; /* 0x00 */
74 u8 ton; /* 0x01 */
75 u8 t1; /* 0x02 */
76 u8 t2w; /* 0x03 */
77 u8 t2r; /* 0x04 */
78 u8 ta; /* 0x05 */
79 u8 trd; /* 0x06 */
80 u8 t4; /* 0x07 */
81 u8 t9; /* 0x08 */
82
83 /* DMA */
84 u8 tm; /* 0x09 */
85 u8 tn; /* 0x0A */
86 u8 td; /* 0x0B */
87 u8 tk; /* 0x0C */
88 u8 tack; /* 0x0D */
89 u8 tenv; /* 0x0E */
90 u8 trp; /* 0x0F */
91 u8 tzah; /* 0x10 */
92 u8 tmli; /* 0x11 */
93 u8 tdvh; /* 0x12 */
94 u8 tdzfs; /* 0x13 */
95 u8 tdvs; /* 0x14 */
96 u8 tcvh; /* 0x15 */
97 u8 tss; /* 0x16 */
98 u8 tcyc; /* 0x17 */
99
100 /* FIFO */
101 u32 fifo32; /* 0x18 */
102 u16 fifo16; /* 0x1C */
103 u8 rsvd0[2];
104 u8 ffill; /* 0x20 */
105 u8 rsvd1[3];
106
107 /* ATA */
108 u8 cr; /* 0x24 */
109 u8 rsvd2[3];
110 u8 isr; /* 0x28 */
111 u8 rsvd3[3];
112 u8 ier; /* 0x2C */
113 u8 rsvd4[3];
114 u8 icr; /* 0x30 */
115 u8 rsvd5[3];
116 u8 falarm; /* 0x34 */
117 u8 rsvd6[106];
118} atac_t;
119
120/*********************************************************************
121* Cross-bar switch (XBS)
122*********************************************************************/
123
124typedef struct xbs {
125 u8 resv0[0x100];
126 u32 prs1; /* XBS Priority Register */
127 u8 resv1[0xC];
128 u32 crs1; /* XBS Control Register */
129 u8 resv2[0xEC];
130 u32 prs2; /* XBS Priority Register */
131 u8 resv3[0xC];
132 u32 crs2; /* XBS Control Register */
133 u8 resv4[0xEC];
134 u32 prs3; /* XBS Priority Register */
135 u8 resv5[0xC];
136 u32 crs3; /* XBS Control Register */
137 u8 resv6[0xEC];
138 u32 prs4; /* XBS Priority Register */
139 u8 resv7[0xC];
140 u32 crs4; /* XBS Control Register */
141 u8 resv8[0xEC];
142 u32 prs5; /* XBS Priority Register */
143 u8 resv9[0xC];
144 u32 crs5; /* XBS Control Register */
145 u8 resv10[0xEC];
146 u32 prs6; /* XBS Priority Register */
147 u8 resv11[0xC];
148 u32 crs6; /* XBS Control Register */
149 u8 resv12[0xEC];
150 u32 prs7; /* XBS Priority Register */
151 u8 resv13[0xC];
152 u32 crs7; /* XBS Control Register */
153} xbs_t;
154
155/*********************************************************************
156* FlexBus Chip Selects (FBCS)
157*********************************************************************/
158
159typedef struct fbcs {
160 u32 csar0; /* Chip-select Address Register */
161 u32 csmr0; /* Chip-select Mask Register */
162 u32 cscr0; /* Chip-select Control Register */
163 u32 csar1; /* Chip-select Address Register */
164 u32 csmr1; /* Chip-select Mask Register */
165 u32 cscr1; /* Chip-select Control Register */
166 u32 csar2; /* Chip-select Address Register */
167 u32 csmr2; /* Chip-select Mask Register */
168 u32 cscr2; /* Chip-select Control Register */
169 u32 csar3; /* Chip-select Address Register */
170 u32 csmr3; /* Chip-select Mask Register */
171 u32 cscr3; /* Chip-select Control Register */
172} fbcs_t;
173
174/*********************************************************************
175* Enhanced DMA (EDMA)
176*********************************************************************/
177
178typedef struct edma {
179 u32 cr;
180 u32 es;
181 u8 resv0[0x6];
182 u16 erq;
183 u8 resv1[0x6];
184 u16 eei;
185 u8 serq;
186 u8 cerq;
187 u8 seei;
188 u8 ceei;
189 u8 cint;
190 u8 cerr;
191 u8 ssrt;
192 u8 cdne;
193 u8 resv2[0x6];
194 u16 intr;
195 u8 resv3[0x6];
196 u16 err;
197 u8 resv4[0xD0];
198 u8 dchpri0;
199 u8 dchpri1;
200 u8 dchpri2;
201 u8 dchpri3;
202 u8 dchpri4;
203 u8 dchpri5;
204 u8 dchpri6;
205 u8 dchpri7;
206 u8 dchpri8;
207 u8 dchpri9;
208 u8 dchpri10;
209 u8 dchpri11;
210 u8 dchpri12;
211 u8 dchpri13;
212 u8 dchpri14;
213 u8 dchpri15;
214 u8 resv5[0xEF0];
215 u32 tcd0_saddr;
216 u16 tcd0_attr;
217 u16 tcd0_soff;
218 u32 tcd0_nbytes;
219 u32 tcd0_slast;
220 u32 tcd0_daddr;
221 union {
222 u16 tcd0_citer_elink;
223 u16 tcd0_citer;
224 };
225 u16 tcd0_doff;
226 u32 tcd0_dlast_sga;
227 union {
228 u16 tcd0_biter_elink;
229 u16 tcd0_biter;
230 };
231 u16 tcd0_csr;
232 u32 tcd1_saddr;
233 u16 tcd1_attr;
234 u16 tcd1_soff;
235 u32 tcd1_nbytes;
236 u32 tcd1_slast;
237 u32 tcd1_daddr;
238 union {
239 u16 tcd1_citer_elink;
240 u16 tcd1_citer;
241 };
242 u16 tcd1_doff;
243 u32 tcd1_dlast_sga;
244 union {
245 u16 tcd1_biter;
246 u16 tcd1_biter_elink;
247 };
248 u16 tcd1_csr;
249 u32 tcd2_saddr;
250 u16 tcd2_attr;
251 u16 tcd2_soff;
252 u32 tcd2_nbytes;
253 u32 tcd2_slast;
254 u32 tcd2_daddr;
255 union {
256 u16 tcd2_citer;
257 u16 tcd2_citer_elink;
258 };
259 u16 tcd2_doff;
260 u32 tcd2_dlast_sga;
261 union {
262 u16 tcd2_biter_elink;
263 u16 tcd2_biter;
264 };
265 u16 tcd2_csr;
266 u32 tcd3_saddr;
267 u16 tcd3_attr;
268 u16 tcd3_soff;
269 u32 tcd3_nbytes;
270 u32 tcd3_slast;
271 u32 tcd3_daddr;
272 union {
273 u16 tcd3_citer;
274 u16 tcd3_citer_elink;
275 };
276 u16 tcd3_doff;
277 u32 tcd3_dlast_sga;
278 union {
279 u16 tcd3_biter_elink;
280 u16 tcd3_biter;
281 };
282 u16 tcd3_csr;
283 u32 tcd4_saddr;
284 u16 tcd4_attr;
285 u16 tcd4_soff;
286 u32 tcd4_nbytes;
287 u32 tcd4_slast;
288 u32 tcd4_daddr;
289 union {
290 u16 tcd4_citer;
291 u16 tcd4_citer_elink;
292 };
293 u16 tcd4_doff;
294 u32 tcd4_dlast_sga;
295 union {
296 u16 tcd4_biter;
297 u16 tcd4_biter_elink;
298 };
299 u16 tcd4_csr;
300 u32 tcd5_saddr;
301 u16 tcd5_attr;
302 u16 tcd5_soff;
303 u32 tcd5_nbytes;
304 u32 tcd5_slast;
305 u32 tcd5_daddr;
306 union {
307 u16 tcd5_citer;
308 u16 tcd5_citer_elink;
309 };
310 u16 tcd5_doff;
311 u32 tcd5_dlast_sga;
312 union {
313 u16 tcd5_biter_elink;
314 u16 tcd5_biter;
315 };
316 u16 tcd5_csr;
317 u32 tcd6_saddr;
318 u16 tcd6_attr;
319 u16 tcd6_soff;
320 u32 tcd6_nbytes;
321 u32 tcd6_slast;
322 u32 tcd6_daddr;
323 union {
324 u16 tcd6_citer;
325 u16 tcd6_citer_elink;
326 };
327 u16 tcd6_doff;
328 u32 tcd6_dlast_sga;
329 union {
330 u16 tcd6_biter_elink;
331 u16 tcd6_biter;
332 };
333 u16 tcd6_csr;
334 u32 tcd7_saddr;
335 u16 tcd7_attr;
336 u16 tcd7_soff;
337 u32 tcd7_nbytes;
338 u32 tcd7_slast;
339 u32 tcd7_daddr;
340 union {
341 u16 tcd7_citer;
342 u16 tcd7_citer_elink;
343 };
344 u16 tcd7_doff;
345 u32 tcd7_dlast_sga;
346 union {
347 u16 tcd7_biter_elink;
348 u16 tcd7_biter;
349 };
350 u16 tcd7_csr;
351 u32 tcd8_saddr;
352 u16 tcd8_attr;
353 u16 tcd8_soff;
354 u32 tcd8_nbytes;
355 u32 tcd8_slast;
356 u32 tcd8_daddr;
357 union {
358 u16 tcd8_citer;
359 u16 tcd8_citer_elink;
360 };
361 u16 tcd8_doff;
362 u32 tcd8_dlast_sga;
363 union {
364 u16 tcd8_biter_elink;
365 u16 tcd8_biter;
366 };
367 u16 tcd8_csr;
368 u32 tcd9_saddr;
369 u16 tcd9_attr;
370 u16 tcd9_soff;
371 u32 tcd9_nbytes;
372 u32 tcd9_slast;
373 u32 tcd9_daddr;
374 union {
375 u16 tcd9_citer_elink;
376 u16 tcd9_citer;
377 };
378 u16 tcd9_doff;
379 u32 tcd9_dlast_sga;
380 union {
381 u16 tcd9_biter_elink;
382 u16 tcd9_biter;
383 };
384 u16 tcd9_csr;
385 u32 tcd10_saddr;
386 u16 tcd10_attr;
387 u16 tcd10_soff;
388 u32 tcd10_nbytes;
389 u32 tcd10_slast;
390 u32 tcd10_daddr;
391 union {
392 u16 tcd10_citer_elink;
393 u16 tcd10_citer;
394 };
395 u16 tcd10_doff;
396 u32 tcd10_dlast_sga;
397 union {
398 u16 tcd10_biter;
399 u16 tcd10_biter_elink;
400 };
401 u16 tcd10_csr;
402 u32 tcd11_saddr;
403 u16 tcd11_attr;
404 u16 tcd11_soff;
405 u32 tcd11_nbytes;
406 u32 tcd11_slast;
407 u32 tcd11_daddr;
408 union {
409 u16 tcd11_citer;
410 u16 tcd11_citer_elink;
411 };
412 u16 tcd11_doff;
413 u32 tcd11_dlast_sga;
414 union {
415 u16 tcd11_biter;
416 u16 tcd11_biter_elink;
417 };
418 u16 tcd11_csr;
419 u32 tcd12_saddr;
420 u16 tcd12_attr;
421 u16 tcd12_soff;
422 u32 tcd12_nbytes;
423 u32 tcd12_slast;
424 u32 tcd12_daddr;
425 union {
426 u16 tcd12_citer;
427 u16 tcd12_citer_elink;
428 };
429 u16 tcd12_doff;
430 u32 tcd12_dlast_sga;
431 union {
432 u16 tcd12_biter;
433 u16 tcd12_biter_elink;
434 };
435 u16 tcd12_csr;
436 u32 tcd13_saddr;
437 u16 tcd13_attr;
438 u16 tcd13_soff;
439 u32 tcd13_nbytes;
440 u32 tcd13_slast;
441 u32 tcd13_daddr;
442 union {
443 u16 tcd13_citer_elink;
444 u16 tcd13_citer;
445 };
446 u16 tcd13_doff;
447 u32 tcd13_dlast_sga;
448 union {
449 u16 tcd13_biter_elink;
450 u16 tcd13_biter;
451 };
452 u16 tcd13_csr;
453 u32 tcd14_saddr;
454 u16 tcd14_attr;
455 u16 tcd14_soff;
456 u32 tcd14_nbytes;
457 u32 tcd14_slast;
458 u32 tcd14_daddr;
459 union {
460 u16 tcd14_citer;
461 u16 tcd14_citer_elink;
462 };
463 u16 tcd14_doff;
464 u32 tcd14_dlast_sga;
465 union {
466 u16 tcd14_biter_elink;
467 u16 tcd14_biter;
468 };
469 u16 tcd14_csr;
470 u32 tcd15_saddr;
471 u16 tcd15_attr;
472 u16 tcd15_soff;
473 u32 tcd15_nbytes;
474 u32 tcd15_slast;
475 u32 tcd15_daddr;
476 union {
477 u16 tcd15_citer_elink;
478 u16 tcd15_citer;
479 };
480 u16 tcd15_doff;
481 u32 tcd15_dlast_sga;
482 union {
483 u16 tcd15_biter;
484 u16 tcd15_biter_elink;
485 };
486 u16 tcd15_csr;
487} edma_t;
488
489/*********************************************************************
490* Interrupt Controller (INTC)
491*********************************************************************/
492
493typedef struct int0_ctrl {
494 u32 iprh0; /* 0x00 Pending Register High */
495 u32 iprl0; /* 0x04 Pending Register Low */
496 u32 imrh0; /* 0x08 Mask Register High */
497 u32 imrl0; /* 0x0C Mask Register Low */
498 u32 frch0; /* 0x10 Force Register High */
499 u32 frcl0; /* 0x14 Force Register Low */
500 u16 res1; /* 0x18 - 0x19 */
501 u16 icfg0; /* 0x1A Configuration Register */
502 u8 simr0; /* 0x1C Set Interrupt Mask */
503 u8 cimr0; /* 0x1D Clear Interrupt Mask */
504 u8 clmask0; /* 0x1E Current Level Mask */
505 u8 slmask; /* 0x1F Saved Level Mask */
506 u32 res2[8]; /* 0x20 - 0x3F */
507 u8 icr0[64]; /* 0x40 - 0x7F Control registers */
508 u32 res3[24]; /* 0x80 - 0xDF */
509 u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
510 u8 res4[3]; /* 0xE1 - 0xE3 */
511 u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
512 u8 res5[3]; /* 0xE5 - 0xE7 */
513 u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
514 u8 res6[3]; /* 0xE9 - 0xEB */
515 u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
516 u8 res7[3]; /* 0xED - 0xEF */
517 u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
518 u8 res8[3]; /* 0xF1 - 0xF3 */
519 u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
520 u8 res9[3]; /* 0xF5 - 0xF7 */
521 u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
522 u8 resa[3]; /* 0xF9 - 0xFB */
523 u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
524 u8 resb[3]; /* 0xFD - 0xFF */
525} int0_t;
526
527typedef struct int1_ctrl {
528 /* Interrupt Controller 1 */
529 u32 iprh1; /* 0x00 Pending Register High */
530 u32 iprl1; /* 0x04 Pending Register Low */
531 u32 imrh1; /* 0x08 Mask Register High */
532 u32 imrl1; /* 0x0C Mask Register Low */
533 u32 frch1; /* 0x10 Force Register High */
534 u32 frcl1; /* 0x14 Force Register Low */
535 u16 res1; /* 0x18 */
536 u16 icfg1; /* 0x1A Configuration Register */
537 u8 simr1; /* 0x1C Set Interrupt Mask */
538 u8 cimr1; /* 0x1D Clear Interrupt Mask */
539 u16 res2; /* 0x1E - 0x1F */
540 u32 res3[8]; /* 0x20 - 0x3F */
541 u8 icr1[64]; /* 0x40 - 0x7F */
542 u32 res4[24]; /* 0x80 - 0xDF */
543 u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
544 u8 res5[3]; /* 0xE1 - 0xE3 */
545 u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
546 u8 res6[3]; /* 0xE5 - 0xE7 */
547 u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
548 u8 res7[3]; /* 0xE9 - 0xEB */
549 u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
550 u8 res8[3]; /* 0xED - 0xEF */
551 u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
552 u8 res9[3]; /* 0xF1 - 0xF3 */
553 u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
554 u8 resa[3]; /* 0xF5 - 0xF7 */
555 u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
556 u8 resb[3]; /* 0xF9 - 0xFB */
557 u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
558 u8 resc[3]; /* 0xFD - 0xFF */
559} int1_t;
560
561/*********************************************************************
562* Global Interrupt Acknowledge (IACK)
563*********************************************************************/
564
565typedef struct iack {
566 u8 resv0[0xE0];
567 u8 gswiack;
568 u8 resv1[0x3];
569 u8 gl1iack;
570 u8 resv2[0x3];
571 u8 gl2iack;
572 u8 resv3[0x3];
573 u8 gl3iack;
574 u8 resv4[0x3];
575 u8 gl4iack;
576 u8 resv5[0x3];
577 u8 gl5iack;
578 u8 resv6[0x3];
579 u8 gl6iack;
580 u8 resv7[0x3];
581 u8 gl7iack;
582} iack_t;
583
584/*********************************************************************
585* DMA Serial Peripheral Interface (DSPI)
586*********************************************************************/
587
588typedef struct dspi {
589 u32 dmcr;
590 u8 resv0[0x4];
591 u32 dtcr;
592 u32 dctar0;
593 u32 dctar1;
594 u32 dctar2;
595 u32 dctar3;
596 u32 dctar4;
597 u32 dctar5;
598 u32 dctar6;
599 u32 dctar7;
600 u32 dsr;
601 u32 dirsr;
602 u32 dtfr;
603 u32 drfr;
604 u32 dtfdr0;
605 u32 dtfdr1;
606 u32 dtfdr2;
607 u32 dtfdr3;
608 u8 resv1[0x30];
609 u32 drfdr0;
610 u32 drfdr1;
611 u32 drfdr2;
612 u32 drfdr3;
613} dspi_t;
614
615/*********************************************************************
616* Edge Port Module (EPORT)
617*********************************************************************/
618
619typedef struct eport {
620 u16 eppar;
621 u8 epddr;
622 u8 epier;
623 u8 epdr;
624 u8 eppdr;
625 u8 epfr;
626} eport_t;
627
628/*********************************************************************
629* Watchdog Timer Modules (WTM)
630*********************************************************************/
631
632typedef struct wtm {
633 u16 wcr;
634 u16 wmr;
635 u16 wcntr;
636 u16 wsr;
637} wtm_t;
638
639/*********************************************************************
640* Serial Boot Facility (SBF)
641*********************************************************************/
642
643typedef struct sbf {
644 u8 resv0[0x18];
645 u16 sbfsr; /* Serial Boot Facility Status Register */
646 u8 resv1[0x6];
647 u16 sbfcr; /* Serial Boot Facility Control Register */
648} sbf_t;
649
650/*********************************************************************
651* Reset Controller Module (RCM)
652*********************************************************************/
653
654typedef struct rcm {
655 u8 rcr;
656 u8 rsr;
657} rcm_t;
658
659/*********************************************************************
660* Chip Configuration Module (CCM)
661*********************************************************************/
662
663typedef struct ccm {
664 u8 ccm_resv0[0x4];
665 u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
666 u8 resv1[0x2];
667 u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
668 u16 cir; /* Chip Identification Register (Read-only) */
669 u8 resv2[0x4];
670 u16 misccr; /* Miscellaneous Control Register */
671 u16 cdr; /* Clock Divider Register */
672 u16 uocsr; /* USB On-the-Go Controller Status Register */
673} ccm_t;
674
675/*********************************************************************
676* General Purpose I/O Module (GPIO)
677*********************************************************************/
678
679typedef struct gpio {
680 u8 podr_fec0h; /* FEC0 High Port Output Data Register */
681 u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
682 u8 podr_ssi; /* SSI Port Output Data Register */
683 u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
684 u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
685 u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
686 u8 podr_dma; /* DMA Port Output Data Register */
687 u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
688 u8 resv0[0x1];
689 u8 podr_uart; /* UART Port Output Data Register */
690 u8 podr_dspi; /* DSPI Port Output Data Register */
691 u8 podr_timer; /* Timer Port Output Data Register */
692 u8 podr_pci; /* PCI Port Output Data Register */
693 u8 podr_usb; /* USB Port Output Data Register */
694 u8 podr_atah; /* ATA High Port Output Data Register */
695 u8 podr_atal; /* ATA Low Port Output Data Register */
696 u8 podr_fec1h; /* FEC1 High Port Output Data Register */
697 u8 podr_fec1l; /* FEC1 Low Port Output Data Register */
698 u8 resv1[0x2];
699 u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */
700 u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
701 u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
702 u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */
703 u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */
704 u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */
705 u8 pddr_ssi; /* SSI Port Data Direction Register */
706 u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */
707 u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */
708 u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */
709 u8 pddr_dma; /* DMA Port Data Direction Register */
710 u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */
711 u8 resv2[0x1];
712 u8 pddr_uart; /* UART Port Data Direction Register */
713 u8 pddr_dspi; /* DSPI Port Data Direction Register */
714 u8 pddr_timer; /* Timer Port Data Direction Register */
715 u8 pddr_pci; /* PCI Port Data Direction Register */
716 u8 pddr_usb; /* USB Port Data Direction Register */
717 u8 pddr_atah; /* ATA High Port Data Direction Register */
718 u8 pddr_atal; /* ATA Low Port Data Direction Register */
719 u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */
720 u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */
721 u8 resv3[0x2];
722 u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */
723 u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */
724 u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */
725 u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */
726 u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */
727 u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
728 u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */
729 u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */
730 u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */
731 u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */
732 u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */
733 u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */
734 u8 resv4[0x1];
735 u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */
736 u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */
737 u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */
738 u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */
739 u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */
740 u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */
741 u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */
742 u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */
743 u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */
744 u8 resv5[0x2];
745 u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */
746 u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */
747 u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
748 u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */
749 u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
750 u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */
751 u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
752 u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
753 u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
754 u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
755 u8 pclrr_dma; /* DMA Port Clear Output Data Register */
756 u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
757 u8 resv6[0x1];
758 u8 pclrr_uart; /* UART Port Clear Output Data Register */
759 u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
760 u8 pclrr_timer; /* Timer Port Clear Output Data Register */
761 u8 pclrr_pci; /* PCI Port Clear Output Data Register */
762 u8 pclrr_usb; /* USB Port Clear Output Data Register */
763 u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
764 u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
765 u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
766 u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
767 u8 resv7[0x2];
768 u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
769 u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
770 u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
771 u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */
772 u8 par_fec; /* FEC Pin Assignment Register */
773 u8 par_dma; /* DMA Pin Assignment Register */
774 u8 par_fbctl; /* Flexbus Control Pin Assignment Register */
775 u8 par_dspi; /* DSPI Pin Assignment Register */
776 u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */
777 u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */
778 u8 par_timer; /* Time Pin Assignment Register */
779 u8 par_usb; /* USB Pin Assignment Register */
780 u8 resv8[0x1];
781 u8 par_uart; /* UART Pin Assignment Register */
782 u16 par_feci2c; /* FEC / I2C Pin Assignment Register */
783 u16 par_ssi; /* SSI Pin Assignment Register */
784 u16 par_ata; /* ATA Pin Assignment Register */
785 u8 par_irq; /* IRQ Pin Assignment Register */
786 u8 resv9[0x1];
787 u16 par_pci; /* PCI Pin Assignment Register */
788 u8 mscr_sdram; /* SDRAM Mode Select Control Register */
789 u8 mscr_pci; /* PCI Mode Select Control Register */
790 u8 resv10[0x2];
791 u8 dscr_i2c; /* I2C Drive Strength Control Register */
792 u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */
793 u8 dscr_fec; /* FEC Drive Strength Control Register */
794 u8 dscr_uart; /* UART Drive Strength Control Register */
795 u8 dscr_dspi; /* DSPI Drive Strength Control Register */
796 u8 dscr_timer; /* TIMER Drive Strength Control Register */
797 u8 dscr_ssi; /* SSI Drive Strength Control Register */
798 u8 dscr_dma; /* DMA Drive Strength Control Register */
799 u8 dscr_debug; /* DEBUG Drive Strength Control Register */
800 u8 dscr_reset; /* RESET Drive Strength Control Register */
801 u8 dscr_irq; /* IRQ Drive Strength Control Register */
802 u8 dscr_usb; /* USB Drive Strength Control Register */
803 u8 dscr_ata; /* ATA Drive Strength Control Register */
804} gpio_t;
805
806/*********************************************************************
807* Random Number Generator (RNG)
808*********************************************************************/
809
810typedef struct rng {
811 u32 rngcr;
812 u32 rngsr;
813 u32 rnger;
814 u32 rngout;
815} rng_t;
816
817/*********************************************************************
818* SDRAM Controller (SDRAMC)
819*********************************************************************/
820
821typedef struct sdramc {
822 u32 sdmr; /* SDRAM Mode/Extended Mode Register */
823 u32 sdcr; /* SDRAM Control Register */
824 u32 sdcfg1; /* SDRAM Configuration Register 1 */
825 u32 sdcfg2; /* SDRAM Chip Select Register */
826 u8 resv0[0x100];
827 u32 sdcs0; /* SDRAM Mode/Extended Mode Register */
828 u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
829} sdramc_t;
830
831/*********************************************************************
832* Synchronous Serial Interface (SSI)
833*********************************************************************/
834
835typedef struct ssi {
836 u32 tx0;
837 u32 tx1;
838 u32 rx0;
839 u32 rx1;
840 u32 cr;
841 u32 isr;
842 u32 ier;
843 u32 tcr;
844 u32 rcr;
845 u32 ccr;
846 u8 resv0[0x4];
847 u32 fcsr;
848 u8 resv1[0x8];
849 u32 acr;
850 u32 acadd;
851 u32 acdat;
852 u32 atag;
853 u32 tmask;
854 u32 rmask;
855} ssi_t;
856
857/*********************************************************************
858* Phase Locked Loop (PLL)
859*********************************************************************/
860
861typedef struct pll {
862 u32 pcr; /* PLL Control Register */
863 u32 psr; /* PLL Status Register */
864} pll_t;
865
866typedef struct pci {
867 u32 idr; /* 0x00 Device Id / Vendor Id Register */
868 u32 scr; /* 0x04 Status / command Register */
869 u32 ccrir; /* 0x08 Class Code / Revision Id Register */
870 u32 cr1; /* 0x0c Configuration 1 Register */
871 u32 bar0; /* 0x10 Base address register 0 Register */
872 u32 bar1; /* 0x14 Base address register 1 Register */
873 u32 bar2; /* 0x18 Base address register 2 Register */
874 u32 bar3; /* 0x1c Base address register 3 Register */
875 u32 bar4; /* 0x20 Base address register 4 Register */
876 u32 bar5; /* 0x24 Base address register 5 Register */
877 u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */
878 u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */
879 u32 erbar; /* 0x30 Expansion ROM Base Address Register */
880 u32 cpr; /* 0x34 Capabilities Pointer Register */
881 u32 rsvd1; /* 0x38 */
882 u32 cr2; /* 0x3c Configuration Register 2 */
883 u32 rsvd2[8]; /* 0x40 - 0x5f */
884
885 /* General control / status registers */
886 u32 gscr; /* 0x60 Global Status / Control Register */
887 u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */
888 u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */
889 u32 tcr1; /* 0x6c Target Control 1 Register */
890 u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */
891 u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */
892 u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */
893 u32 rsvd3; /* 0x7c */
894 u32 iwcr; /* 0x80 Initiator Window Configuration Register */
895 u32 icr; /* 0x84 Initiator Control Register */
896 u32 isr; /* 0x88 Initiator Status Register */
897 u32 tcr2; /* 0x8c Target Control 2 Register */
898 u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */
899 u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */
900 u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */
901 u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */
902 u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */
903 u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */
904 u32 intr; /* 0xa8 Interrupt Register */
905 u32 rsvd4[19]; /* 0xac - 0xf7 */
906 u32 car; /* 0xf8 Configuration Address Register */
907} pci_t;
908
909typedef struct pci_arbiter {
910 /* Pci Arbiter Registers */
911 union {
912 u32 acr; /* Arbiter Control Register */
913 u32 asr; /* Arbiter Status Register */
914 };
915} pciarb_t;
916
917/* Register read/write struct */
918typedef struct scm1 {
919 u32 mpr; /* 0x00 Master Privilege Register */
920 u32 rsvd1[7];
921 u32 pacra; /* 0x20 Peripheral Access Control Register A */
922 u32 pacrb; /* 0x24 Peripheral Access Control Register B */
923 u32 pacrc; /* 0x28 Peripheral Access Control Register C */
924 u32 pacrd; /* 0x2C Peripheral Access Control Register D */
925 u32 rsvd2[4];
926 u32 pacre; /* 0x40 Peripheral Access Control Register E */
927 u32 pacrf; /* 0x44 Peripheral Access Control Register F */
928 u32 pacrg; /* 0x48 Peripheral Access Control Register G */
929} scm1_t;
930/********************************************************************/
931
932typedef struct rtcex {
933 u32 rsvd1[3];
934 u32 gocu;
935 u32 gocl;
936} rtcex_t;
937#endif /* __IMMAP_5445X__ */