Jagan Teki | 8967dea | 2023-01-30 20:27:45 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2021 Rockchip Electronics Co., Ltd |
| 4 | * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <spl.h> |
| 9 | #include <asm/armv8/mmu.h> |
| 10 | #include <asm/io.h> |
Jonas Karlman | afe8635f | 2023-03-14 00:38:30 +0000 | [diff] [blame] | 11 | #include <asm/arch-rockchip/bootrom.h> |
Jagan Teki | 8967dea | 2023-01-30 20:27:45 +0530 | [diff] [blame] | 12 | #include <asm/arch-rockchip/hardware.h> |
| 13 | #include <asm/arch-rockchip/ioc_rk3588.h> |
| 14 | |
| 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
| 17 | #define FIREWALL_DDR_BASE 0xfe030000 |
| 18 | #define FW_DDR_MST5_REG 0x54 |
| 19 | #define FW_DDR_MST13_REG 0x74 |
| 20 | #define FW_DDR_MST21_REG 0x94 |
| 21 | #define FW_DDR_MST26_REG 0xa8 |
| 22 | #define FW_DDR_MST27_REG 0xac |
| 23 | #define FIREWALL_SYSMEM_BASE 0xfe038000 |
| 24 | #define FW_SYSM_MST5_REG 0x54 |
| 25 | #define FW_SYSM_MST13_REG 0x74 |
| 26 | #define FW_SYSM_MST21_REG 0x94 |
| 27 | #define FW_SYSM_MST26_REG 0xa8 |
| 28 | #define FW_SYSM_MST27_REG 0xac |
| 29 | |
| 30 | #define PMU1_IOC_BASE 0xfd5f0000 |
| 31 | #define PMU2_IOC_BASE 0xfd5f4000 |
| 32 | |
| 33 | #define BUS_IOC_BASE 0xfd5f8000 |
| 34 | #define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40 |
| 35 | #define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48 |
| 36 | #define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58 |
| 37 | #define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c |
| 38 | #define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60 |
| 39 | |
Jonas Karlman | afe8635f | 2023-03-14 00:38:30 +0000 | [diff] [blame] | 40 | const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { |
| 41 | [BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000", |
| 42 | [BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b0000/flash@0", |
| 43 | [BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000", |
Jonas Karlman | adb7894 | 2023-05-18 15:39:30 +0000 | [diff] [blame] | 44 | [BROM_BOOTSOURCE_SPINOR_RK3588] = "/spi@fe2b0000/flash@0", |
Jonas Karlman | afe8635f | 2023-03-14 00:38:30 +0000 | [diff] [blame] | 45 | }; |
| 46 | |
Jagan Teki | 8967dea | 2023-01-30 20:27:45 +0530 | [diff] [blame] | 47 | static struct mm_region rk3588_mem_map[] = { |
| 48 | { |
| 49 | .virt = 0x0UL, |
| 50 | .phys = 0x0UL, |
| 51 | .size = 0xf0000000UL, |
| 52 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 53 | PTE_BLOCK_INNER_SHARE |
| 54 | }, { |
| 55 | .virt = 0xf0000000UL, |
| 56 | .phys = 0xf0000000UL, |
| 57 | .size = 0x10000000UL, |
| 58 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 59 | PTE_BLOCK_NON_SHARE | |
| 60 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 61 | }, { |
| 62 | .virt = 0x900000000, |
| 63 | .phys = 0x900000000, |
| 64 | .size = 0x150000000, |
| 65 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 66 | PTE_BLOCK_NON_SHARE | |
| 67 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 68 | }, { |
| 69 | /* List terminator */ |
| 70 | 0, |
| 71 | } |
| 72 | }; |
| 73 | |
| 74 | struct mm_region *mem_map = rk3588_mem_map; |
| 75 | |
| 76 | /* GPIO0B_IOMUX_SEL_H */ |
| 77 | enum { |
| 78 | GPIO0B5_SHIFT = 4, |
| 79 | GPIO0B5_MASK = GENMASK(7, 4), |
| 80 | GPIO0B5_REFER = 8, |
| 81 | GPIO0B5_UART2_TX_M0 = 10, |
| 82 | |
| 83 | GPIO0B6_SHIFT = 8, |
| 84 | GPIO0B6_MASK = GENMASK(11, 8), |
| 85 | GPIO0B6_REFER = 8, |
| 86 | GPIO0B6_UART2_RX_M0 = 10, |
| 87 | }; |
| 88 | |
| 89 | void board_debug_uart_init(void) |
| 90 | { |
| 91 | __maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE; |
| 92 | static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE; |
| 93 | |
| 94 | /* Refer to BUS_IOC */ |
| 95 | rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h, |
| 96 | GPIO0B6_MASK | GPIO0B5_MASK, |
| 97 | GPIO0B6_REFER << GPIO0B6_SHIFT | |
| 98 | GPIO0B5_REFER << GPIO0B5_SHIFT); |
| 99 | |
| 100 | /* UART2_M0 Switch iomux */ |
| 101 | rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h, |
| 102 | GPIO0B6_MASK | GPIO0B5_MASK, |
| 103 | GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT | |
| 104 | GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT); |
| 105 | } |
| 106 | |
| 107 | #ifdef CONFIG_SPL_BUILD |
| 108 | void rockchip_stimer_init(void) |
| 109 | { |
| 110 | /* If Timer already enabled, don't re-init it */ |
| 111 | u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4); |
| 112 | |
| 113 | if (reg & 0x1) |
| 114 | return; |
| 115 | |
| 116 | asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); |
| 117 | writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14); |
| 118 | writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18); |
| 119 | writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4); |
| 120 | } |
| 121 | #endif |
| 122 | |
| 123 | #ifndef CONFIG_TPL_BUILD |
| 124 | int arch_cpu_init(void) |
| 125 | { |
| 126 | #ifdef CONFIG_SPL_BUILD |
| 127 | int secure_reg; |
| 128 | |
| 129 | /* Set the SDMMC eMMC crypto_ns FSPI access secure area */ |
| 130 | secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG); |
| 131 | secure_reg &= 0xffff; |
| 132 | writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG); |
| 133 | secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG); |
| 134 | secure_reg &= 0xffff; |
| 135 | writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG); |
| 136 | secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG); |
| 137 | secure_reg &= 0xffff; |
| 138 | writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG); |
| 139 | secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG); |
| 140 | secure_reg &= 0xffff; |
| 141 | writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG); |
| 142 | secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG); |
| 143 | secure_reg &= 0xffff0000; |
| 144 | writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG); |
| 145 | |
| 146 | secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG); |
| 147 | secure_reg &= 0xffff; |
| 148 | writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG); |
| 149 | secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG); |
| 150 | secure_reg &= 0xffff; |
| 151 | writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG); |
| 152 | secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG); |
| 153 | secure_reg &= 0xffff; |
| 154 | writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG); |
| 155 | secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG); |
| 156 | secure_reg &= 0xffff; |
| 157 | writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG); |
| 158 | secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG); |
| 159 | secure_reg &= 0xffff0000; |
| 160 | writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG); |
| 161 | #endif |
| 162 | |
| 163 | return 0; |
| 164 | } |
| 165 | #endif |