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Priyanka Jainfd45ca02018-11-28 13:04:27 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +05303 * Copyright 2018, 2020 NXP
Priyanka Jainfd45ca02018-11-28 13:04:27 +00004 *
5 */
6
7#include <common.h>
Priyanka Jainfd45ca02018-11-28 13:04:27 +00008#include <netdev.h>
Priyanka Jainfd45ca02018-11-28 13:04:27 +00009#include <exports.h>
Priyanka Jainfd45ca02018-11-28 13:04:27 +000010#include <fsl-mc/fsl_mc.h>
Priyanka Jainfd45ca02018-11-28 13:04:27 +000011
12DECLARE_GLOBAL_DATA_PTR;
13
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090014int board_eth_init(struct bd_info *bis)
Priyanka Jainfd45ca02018-11-28 13:04:27 +000015{
Priyanka Jainfd45ca02018-11-28 13:04:27 +000016#ifdef CONFIG_PHY_AQUANTIA
17 /*
18 * Export functions to be used by AQ firmware
19 * upload application
20 */
21 gd->jt->strcpy = strcpy;
22 gd->jt->mdelay = mdelay;
23 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
24 gd->jt->phy_find_by_mask = phy_find_by_mask;
25 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
26 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
27#endif
28 return pci_eth_init(bis);
29}
30
31#if defined(CONFIG_RESET_PHY_R)
32void reset_phy(void)
33{
34#if defined(CONFIG_FSL_MC_ENET)
35 mc_env_boot();
36#endif
37}
38#endif /* CONFIG_RESET_PHY_R */