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Peng Fanc47e09d2019-12-30 17:46:21 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <common.h>
Simon Glassed38aef2020-05-10 11:40:03 -06007#include <env.h>
Peng Fanc47e09d2019-12-30 17:46:21 +08008#include <errno.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Peng Fan4f0c97b2020-12-25 16:16:34 +080010#include <miiphy.h>
11#include <netdev.h>
12#include <linux/delay.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Peng Fanc47e09d2019-12-30 17:46:21 +080014#include <asm/mach-imx/iomux-v3.h>
15#include <asm-generic/gpio.h>
16#include <asm/arch/imx8mp_pins.h>
Peng Fan4f0c97b2020-12-25 16:16:34 +080017#include <asm/arch/clock.h>
Peng Fanc47e09d2019-12-30 17:46:21 +080018#include <asm/arch/sys_proto.h>
19#include <asm/mach-imx/gpio.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
Peng Fan4f0c97b2020-12-25 16:16:34 +080023static void setup_fec(void)
24{
25 struct iomuxc_gpr_base_regs *gpr =
26 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
27
28 /* Enable RGMII TX clk output */
29 setbits_le32(&gpr->gpr[1], BIT(22));
30}
31
Peng Fan4f0c97b2020-12-25 16:16:34 +080032#if CONFIG_IS_ENABLED(NET)
33int board_phy_config(struct phy_device *phydev)
Peng Fanc47e09d2019-12-30 17:46:21 +080034{
Peng Fan4f0c97b2020-12-25 16:16:34 +080035 if (phydev->drv->config)
36 phydev->drv->config(phydev);
Peng Fanc47e09d2019-12-30 17:46:21 +080037 return 0;
38}
Peng Fan4f0c97b2020-12-25 16:16:34 +080039#endif
40
41int board_init(void)
42{
43 int ret = 0;
44
Simon Glassb42427e2023-02-05 17:54:16 -070045 if (IS_ENABLED(CONFIG_FEC_MXC)) {
Peng Fan4f0c97b2020-12-25 16:16:34 +080046 setup_fec();
Ye Li82da0f52021-08-16 18:44:29 +080047 }
Peng Fan4f0c97b2020-12-25 16:16:34 +080048
Peng Fan4f0c97b2020-12-25 16:16:34 +080049 return ret;
50}
Peng Fanc47e09d2019-12-30 17:46:21 +080051
52int board_late_init(void)
53{
54#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
55 env_set("board_name", "EVK");
56 env_set("board_rev", "iMX8MP");
57#endif
58
59 return 0;
60}